Search Results - "VLSI design"

VLSI Design of a Wavelet Processing Core by Sze, Wei Lee, Soon, Chieh Lim

Get full text
Get full text

A VLSI Design Framework with Freeware CAD Tools by Teh, Y. K., Mohd-Yasin, F., Reaz, M. B. I., Kordesch, A.

Get full text

Implementation of VLSI design flow for MIPS-based SOC by Lee, Zhao Min

“…The two phases in the VLSI design flow are front-end design and back end design. …”
Get full text
Get full text

VLSI Design Of A Bit Serial Arithmetic Logic Unit by Lee, Tiong Kiat

Get full text

VLSI Design of a neurohardware processor implementing the Kohonen Neural Network algorithm by Rajah, Avinash

“…Thus, to cater to this need, the VLSI design and implementation of a neurohardware for high-speed pattern recognition is proposed in this research. …”
Get full text
Get full text

Optimization of an Integrated Circuit Device by Improving ITS VLSI Design from RTL to GDSII by Thee, Kang Wei

“…VLSI design flow from RTL to GDSII consists of two phases, namely front-end design and back-end design. …”
Get full text
Get full text

Energy efficient and runtime based approximate computing techniques for image processing applications: an integrated approach covering circuit to algorithmic level by Huang, Junqi

Subjects: Get full text

Crystal controlled CMOS oscillator for 13.56 MHz RFID reader by Motakabber, S. M. A., Ibrahimy, Muhammad Ibn

“…A design procedure of CMOS integrated crystal oscillator for 13.56 MHz RFID is described in detail by using mathematical and Mentor Graphics VLSI design tools ADK-3. The system is designed by using CMOS 0.18 µm foundry rules and Level-3 transistor model. …”
Get full text
Get full text

CAD Automation Module Based On Cell Moving Algorithm For Incremental Placement Timing Optimization by Kan, Mei War

“…This is why ECO remains one of the most influential steps in Very Large Scale Integration (VLSI) design. This thesis describes timing driven incremental placement that uses standard-cell move technique to improve timing of the layout design.…”
Get full text
Get full text

Asic design of a kohonen neural network microchip by Rajah, Avinash, Hani, Mohamed Khalil

“…The 3.3V AMI 0.5um CO5M-D process technology was used to achieve the VLSI design of the computation engine microchip and the entire design adopted the BBX cell based methodology, which is a viable alternative to conventional ASIC methodology.…”
Get full text
Get full text

Design of CMOS tunable image-rejection LNA using active inductor by Ler, Chun Lee, A'ain, Abu Khari, Kordesch, A. V.

Get full text

Parallel Processing Models For Image Processing Problems by Salleh, Shaharuddin, Sanugi, Bahrom

“…In the third problem, we extend the scope to include a strategy for the single-row routing of pins and vias in VLSI design, using our model called the Enhanced Simulated annealing for Single-row Routing (ESSR). …”
Get full text
Get full text

Single-row transformation of complete graphs by Salleh, Shahruddin Hussain, Olariu, Stephan, Sanugi, Bahrom, Aziz, Mohd Ismail Abd

“…Single-row routing is a classical technique in the VLSI design that is known to be NP-complete. We solved this problem earlier using a method called ESSR, and, the same technique is applied to the present work to transform a complete graph into its single-row routing representation. …”
Get full text
Get full text

A new scan design technique based on pre-synthesis thru functions by Chia, Yee Ooi, Fujiwara, Hideo

“…VLSI design has moved from bottom-up design approach to top-down design methodology with the aid of advanced Computer-Aided Design (CAD) technology. …”
Get full text

Fast-lock dual charge pump analog DLL using improved phase frequency detector by Lip-Kai, Soh, Sulaiman, Mohd-Shahiman, Yusoff, Zubaida

Get full text

A genetic algorithm approach to VLSI macro cell non-slicing floorplans using binary tree by Rahim At Samsuddin, H. A., Ab. Rahman, A. A. H., Andaljayalakshmi, G., Ahmad, R. B.

“…A binary tree method for non-slicing tree construction process is utilized for the placement and area optimization of macro-cell layout in very large scaled integrated (VLSI) design. Three different types of genetic algorithms: simple genetic algorithm (SGA), steady-state algorithm (SSGA) and adaptive genetic algorithm (AGA) are employed in order to examine their performances in converging to their global minimums. …”
Get full text

Nano-scale VLSI clock routing module based on useful-skew tree algorithm by Eik Wee, Chew, Heng Sun, Ch'ng, Shaikh-Husin, Nasir, Hani, Mohamed Khalil

“…This way, the computation result of proposed synthesis module can generate a clock signal distribution routing path with minimum wire length and, ensures the reliability of data synchronization for nano-scale VLSI design.…”
Get full text
Get full text

VLSI implementation of full adder-subtractor design by Ahmad, Nabihah, Lim, Yoong Kang

“…Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the major concerns in order to develop an efficient electronic devices. …”
Get full text
Get full text

FPGA-assisted assertion-based verification platform by Mohamad, Nurita, Chia, Yee Ooi, Jwing Teh, Jwing Teh, Paraman, Norlina, Hassan, Hasliza, Ismail, Nordinah

“…It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time.…”
Get full text
Get full text

Design and Synthesis of Mobile Robot Controller using Fuzzy by Islam, Md. Shabiul, Azim, Md. Anwarul, Jahan, Md. Saukat, Othman, Masuri

“…Finally the MRC hardware blocks for VLSI design have been carried out.…”
Get full text
Get full text