Search Results - "VLSI Testing"

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    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) by Singh, Ashutosh Kumar, Bera, A., Rahaman, H., Mathew, J., Pradhan, D.k.

    Published 2009
    Subjects: Get full text
  2. 2
    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

    Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m) by Singh, Ashutosh Kumar, Bera, A., Rahaman, H., Mathew, J., Pradhan, D.

    Published 2009
    Subjects: “…very large scale integration (VLSI) testing…”
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