A new class of sequential circuits with acyclic test generation complexity

This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation proce...

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Main Authors: Ooi, Chia Yee, Fujiwara, Hideo
Format: Conference or Workshop Item
Published: 2006
Online Access:http://eprints.utm.my/9169/
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author Ooi, Chia Yee
Fujiwara, Hideo
author_facet Ooi, Chia Yee
Fujiwara, Hideo
author_sort Ooi, Chia Yee
building UTeM Institutional Repository
collection Online Access
description This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
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format Conference or Workshop Item
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institution Universiti Teknologi Malaysia
institution_category Local University
last_indexed 2025-11-15T21:04:07Z
publishDate 2006
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spelling utm-91692009-07-27T03:14:22Z http://eprints.utm.my/9169/ A new class of sequential circuits with acyclic test generation complexity Ooi, Chia Yee Fujiwara, Hideo This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose test generation complexity is equivalent to that of the acyclic sequential circuits. We also present a test generation procedure for acyclically testable sequential circuits and elaborate a design-for-test (DFT) method to augment an arbitrary sequential circuit into an acyclically testable sequential circuit. Since the class of acyclically testable sequential circuits is larger than the class of acyclic sequential circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not. 2006 Conference or Workshop Item PeerReviewed Ooi, Chia Yee and Fujiwara, Hideo (2006) A new class of sequential circuits with acyclic test generation complexity. In: 24th IEEE International Conference on Computer Design (ICCD'06), 1-4 Oct. 2007 . http://dx.doi.org/10.1109/ICCD.2006.4380851
spellingShingle Ooi, Chia Yee
Fujiwara, Hideo
A new class of sequential circuits with acyclic test generation complexity
title A new class of sequential circuits with acyclic test generation complexity
title_full A new class of sequential circuits with acyclic test generation complexity
title_fullStr A new class of sequential circuits with acyclic test generation complexity
title_full_unstemmed A new class of sequential circuits with acyclic test generation complexity
title_short A new class of sequential circuits with acyclic test generation complexity
title_sort new class of sequential circuits with acyclic test generation complexity
url http://eprints.utm.my/9169/
http://eprints.utm.my/9169/