Characterization of 50 nm MOSFET with dielectric pocket
Characterizat ion of a metal-oxide-semi conductor field effect tran sistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE ) is demonstrated by using 2D numerical simulation. An analysis of 120 nm and 50 nm channel length (LJ wit h DP incorp orated between the chann...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Malaysian Institute of Physics
2007
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| Subjects: | |
| Online Access: | http://eprints.utm.my/8046/ http://eprints.utm.my/8046/2/%5B093-098%5D-zul.pdf |
| _version_ | 1848891607162552320 |
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| author | Fauzan, Zul Atfyi Saad, Ismail Ismail, Razali |
| author_facet | Fauzan, Zul Atfyi Saad, Ismail Ismail, Razali |
| author_sort | Fauzan, Zul Atfyi |
| building | UTeM Institutional Repository |
| collection | Online Access |
| description | Characterizat ion of a metal-oxide-semi conductor field effect tran sistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE ) is demonstrated by using 2D numerical simulation. An analysis of 120 nm and 50 nm channel length (LJ wit h DP incorp orated between the chann el and source/drain has been done successfu lly. The DP has suppressed short channel effect (SCE) witho ut the need s of increasi ng the channel dopin g pro file. With uniform dopi ng of 10" em' and 10' 0 ern' for channel and source/drain region respectively, a reduc tion of 2.5 decade s of leakage current (lOFF) was obtained in MOSFET with DP without altering the drive current (ION) for 120 nm channe l length . A very low leakage current of 0.002 pAl l'm is obtained for DP device with drain voltag e (Vos) of 0.1 V and increase to 18 pAll'm with Vns = l.OV for 120 nm Lg. Th is obtained with drive current of 0.5 rnA and 5 rnA respectively. Meanwhile, with L. = 50 nm, 700 nAll'm leakage current and 1 mAll'm drive current was o bserved. With the same doping profile s, a reduct ion of 1.4 decades of 10 FF was shown by the incorpora tion of DP for Lg = 50 nm. Thus, the incorporation of DP will enhance the electri cal perform ance and give a very good control of the SCE for sca ling the MOSFET in nanometer regime for future developme nt of nanoe lectronics product. |
| first_indexed | 2025-11-15T21:00:39Z |
| format | Article |
| id | utm-8046 |
| institution | Universiti Teknologi Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T21:00:39Z |
| publishDate | 2007 |
| publisher | Malaysian Institute of Physics |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utm-80462017-10-11T01:43:12Z http://eprints.utm.my/8046/ Characterization of 50 nm MOSFET with dielectric pocket Fauzan, Zul Atfyi Saad, Ismail Ismail, Razali TK Electrical engineering. Electronics Nuclear engineering QC Physics Characterizat ion of a metal-oxide-semi conductor field effect tran sistor incorporating dielectric pocket (DP) for suppression of short-channel effect (SCE ) is demonstrated by using 2D numerical simulation. An analysis of 120 nm and 50 nm channel length (LJ wit h DP incorp orated between the chann el and source/drain has been done successfu lly. The DP has suppressed short channel effect (SCE) witho ut the need s of increasi ng the channel dopin g pro file. With uniform dopi ng of 10" em' and 10' 0 ern' for channel and source/drain region respectively, a reduc tion of 2.5 decade s of leakage current (lOFF) was obtained in MOSFET with DP without altering the drive current (ION) for 120 nm channe l length . A very low leakage current of 0.002 pAl l'm is obtained for DP device with drain voltag e (Vos) of 0.1 V and increase to 18 pAll'm with Vns = l.OV for 120 nm Lg. Th is obtained with drive current of 0.5 rnA and 5 rnA respectively. Meanwhile, with L. = 50 nm, 700 nAll'm leakage current and 1 mAll'm drive current was o bserved. With the same doping profile s, a reduct ion of 1.4 decades of 10 FF was shown by the incorpora tion of DP for Lg = 50 nm. Thus, the incorporation of DP will enhance the electri cal perform ance and give a very good control of the SCE for sca ling the MOSFET in nanometer regime for future developme nt of nanoe lectronics product. Malaysian Institute of Physics 2007 Article PeerReviewed text/html en http://eprints.utm.my/8046/2/%5B093-098%5D-zul.pdf Fauzan, Zul Atfyi and Saad, Ismail and Ismail, Razali (2007) Characterization of 50 nm MOSFET with dielectric pocket. Jurnal Fizik Malaysia, 28 (3-4). pp. 93-98. ISSN 0128-0333 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering QC Physics Fauzan, Zul Atfyi Saad, Ismail Ismail, Razali Characterization of 50 nm MOSFET with dielectric pocket |
| title | Characterization of 50 nm MOSFET with dielectric pocket
|
| title_full | Characterization of 50 nm MOSFET with dielectric pocket
|
| title_fullStr | Characterization of 50 nm MOSFET with dielectric pocket
|
| title_full_unstemmed | Characterization of 50 nm MOSFET with dielectric pocket
|
| title_short | Characterization of 50 nm MOSFET with dielectric pocket
|
| title_sort | characterization of 50 nm mosfet with dielectric pocket |
| topic | TK Electrical engineering. Electronics Nuclear engineering QC Physics |
| url | http://eprints.utm.my/8046/ http://eprints.utm.my/8046/2/%5B093-098%5D-zul.pdf |