Verilog design of input/output processor with built-in-self-test
This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. Th...
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| Format: | Thesis |
| Language: | English |
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2007
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| Online Access: | http://eprints.utm.my/5959/ http://eprints.utm.my/5959/1/GohKengHooMFKE2007.pdf |
| _version_ | 1848891161999048704 |
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| author | Goh, Keng Hoo |
| author_facet | Goh, Keng Hoo |
| author_sort | Goh, Keng Hoo |
| building | UTeM Institutional Repository |
| collection | Online Access |
| description | This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. The embedded BIST capability in IOP designed in this project has the objectives to satisfy specified testability requirements and to generate the lowest-cost with the highest performance implementation. Linear Feedback Shift Register (LFSR) is used to replace the expensive testers to generate pseudo random test pattern to IOP while Multiple Input Signature Register (MISR) is able to compact the IOP output response into a manageable signature size. In this project, the designed is coded in Verilog hardware description language at register transfer level (RTL), synthesized using Altera Quartus II using FPFA device from APEC20KE family, RTL level compilation and simulation using Modelsim v6.1b and gate level timing simulation using Modelsim-Altera v6.1g. This project was scheduled for two semester in which the activities to study and determine hardware specifications, requirements, functionalities and Verilog HDL migration were done in first semester whereas activities to design, synthesis, compile, simulate, and validate were carried out in semester 2. IOP with BIST capability contributes additional 30% hardware overhead but is somehow reasonable considering the test performance obtained and the ability of the BIST block provides high fault coverage. |
| first_indexed | 2025-11-15T20:53:34Z |
| format | Thesis |
| id | utm-5959 |
| institution | Universiti Teknologi Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T20:53:34Z |
| publishDate | 2007 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utm-59592018-09-27T04:01:29Z http://eprints.utm.my/5959/ Verilog design of input/output processor with built-in-self-test Goh, Keng Hoo TK Electrical engineering. Electronics Nuclear engineering This project has a final goal of designing an I/O processor (IOP) with embedded built-in-self-test (BIST) capability. The IOP core design was originally design in VHDL modeling has been migrated to Verilog HDL modeling in this project. BIST is one of the most popular test technique used nowadays. The embedded BIST capability in IOP designed in this project has the objectives to satisfy specified testability requirements and to generate the lowest-cost with the highest performance implementation. Linear Feedback Shift Register (LFSR) is used to replace the expensive testers to generate pseudo random test pattern to IOP while Multiple Input Signature Register (MISR) is able to compact the IOP output response into a manageable signature size. In this project, the designed is coded in Verilog hardware description language at register transfer level (RTL), synthesized using Altera Quartus II using FPFA device from APEC20KE family, RTL level compilation and simulation using Modelsim v6.1b and gate level timing simulation using Modelsim-Altera v6.1g. This project was scheduled for two semester in which the activities to study and determine hardware specifications, requirements, functionalities and Verilog HDL migration were done in first semester whereas activities to design, synthesis, compile, simulate, and validate were carried out in semester 2. IOP with BIST capability contributes additional 30% hardware overhead but is somehow reasonable considering the test performance obtained and the ability of the BIST block provides high fault coverage. 2007-04 Thesis NonPeerReviewed application/pdf en http://eprints.utm.my/5959/1/GohKengHooMFKE2007.pdf Goh, Keng Hoo (2007) Verilog design of input/output processor with built-in-self-test. Masters thesis, Universiti Teknologi Malaysia, Faculty of Electrical Engineering. http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:62149 |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Goh, Keng Hoo Verilog design of input/output processor with built-in-self-test |
| title | Verilog design of input/output processor with built-in-self-test |
| title_full | Verilog design of input/output processor with built-in-self-test |
| title_fullStr | Verilog design of input/output processor with built-in-self-test |
| title_full_unstemmed | Verilog design of input/output processor with built-in-self-test |
| title_short | Verilog design of input/output processor with built-in-self-test |
| title_sort | verilog design of input/output processor with built-in-self-test |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utm.my/5959/ http://eprints.utm.my/5959/ http://eprints.utm.my/5959/1/GohKengHooMFKE2007.pdf |