Nano-scale VLSI clock routing module based on useful-skew tree algorithm

Clock routing is critical in nano-scale VLSI circuit design. Clock routing needs to be precise to minimize circuit delay. Clock signals are strongly affected by technology scaling, the long global interconnect lines become highly resistive as line dimensions are decreased. The control of clock skew...

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Main Authors: Eik Wee, Chew, Heng Sun, Ch'ng, Shaikh-Husin, Nasir, Hani, Mohamed Khalil
Format: Article
Language:English
Published: School of Postgraduate Studies, UTM 2006
Subjects:
Online Access:http://eprints.utm.my/1687/
http://eprints.utm.my/1687/1/sh-nasir05_Nano_scale_VLSI.pdf
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author Eik Wee, Chew
Heng Sun, Ch'ng
Shaikh-Husin, Nasir
Hani, Mohamed Khalil
author_facet Eik Wee, Chew
Heng Sun, Ch'ng
Shaikh-Husin, Nasir
Hani, Mohamed Khalil
author_sort Eik Wee, Chew
building UTeM Institutional Repository
collection Online Access
description Clock routing is critical in nano-scale VLSI circuit design. Clock routing needs to be precise to minimize circuit delay. Clock signals are strongly affected by technology scaling, the long global interconnect lines become highly resistive as line dimensions are decreased. The control of clock skew can also severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register. Thus, we propose a clock routing synthesis module that applies non-zero skew (or called useful-skew) method to reduce the system-wide minimum clock period to improve the performance of synchronous digital circuit. We implemented Useful-Skew Tree (UST) algorithm which is based on the deferred-merge embedding (DME) paradigm, as the clock layout synthesis engine. The synthesis module is integrated with the UTM in-house design graph accelerator to enhance the computation performance. The novel contribution of this work is clock skew scheduling is performed simultaneously with clock tree routing. This way, the computation result of proposed synthesis module can generate a clock signal distribution routing path with minimum wire length and, ensures the reliability of data synchronization for nano-scale VLSI design.
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spelling utm-16872011-05-16T09:43:28Z http://eprints.utm.my/1687/ Nano-scale VLSI clock routing module based on useful-skew tree algorithm Eik Wee, Chew Heng Sun, Ch'ng Shaikh-Husin, Nasir Hani, Mohamed Khalil TK Electrical engineering. Electronics Nuclear engineering Clock routing is critical in nano-scale VLSI circuit design. Clock routing needs to be precise to minimize circuit delay. Clock signals are strongly affected by technology scaling, the long global interconnect lines become highly resistive as line dimensions are decreased. The control of clock skew can also severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register. Thus, we propose a clock routing synthesis module that applies non-zero skew (or called useful-skew) method to reduce the system-wide minimum clock period to improve the performance of synchronous digital circuit. We implemented Useful-Skew Tree (UST) algorithm which is based on the deferred-merge embedding (DME) paradigm, as the clock layout synthesis engine. The synthesis module is integrated with the UTM in-house design graph accelerator to enhance the computation performance. The novel contribution of this work is clock skew scheduling is performed simultaneously with clock tree routing. This way, the computation result of proposed synthesis module can generate a clock signal distribution routing path with minimum wire length and, ensures the reliability of data synchronization for nano-scale VLSI design. School of Postgraduate Studies, UTM 2006-07-26 Article NonPeerReviewed application/pdf en http://eprints.utm.my/1687/1/sh-nasir05_Nano_scale_VLSI.pdf Eik Wee, Chew and Heng Sun, Ch'ng and Shaikh-Husin, Nasir and Hani, Mohamed Khalil (2006) Nano-scale VLSI clock routing module based on useful-skew tree algorithm. Regional Postgraduate Conference on Engineering and Science . pp. 269-273.
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Eik Wee, Chew
Heng Sun, Ch'ng
Shaikh-Husin, Nasir
Hani, Mohamed Khalil
Nano-scale VLSI clock routing module based on useful-skew tree algorithm
title Nano-scale VLSI clock routing module based on useful-skew tree algorithm
title_full Nano-scale VLSI clock routing module based on useful-skew tree algorithm
title_fullStr Nano-scale VLSI clock routing module based on useful-skew tree algorithm
title_full_unstemmed Nano-scale VLSI clock routing module based on useful-skew tree algorithm
title_short Nano-scale VLSI clock routing module based on useful-skew tree algorithm
title_sort nano-scale vlsi clock routing module based on useful-skew tree algorithm
topic TK Electrical engineering. Electronics Nuclear engineering
url http://eprints.utm.my/1687/
http://eprints.utm.my/1687/1/sh-nasir05_Nano_scale_VLSI.pdf