FPGA-assisted assertion-based verification platform
In this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. T...
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| Format: | Article |
| Language: | English |
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Faculty of Electronic and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM)
2020
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| Subjects: | |
| Online Access: | http://eprints.uthm.edu.my/6620/ http://eprints.uthm.edu.my/6620/1/J13927_a4acd108d79f171fe2520f39b74e7a1e.pdf |
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| author | Mohamad, Nurita Chia, Yee Ooi Jwing Teh, Jwing Teh Paraman, Norlina Hassan, Hasliza Ismail, Nordinah |
| author_facet | Mohamad, Nurita Chia, Yee Ooi Jwing Teh, Jwing Teh Paraman, Norlina Hassan, Hasliza Ismail, Nordinah |
| author_sort | Mohamad, Nurita |
| building | UTHM Institutional Repository |
| collection | Online Access |
| description | In this paper, field programmable gate array
(FPGA)-assisted verification platform is devised to enhance the
assertion-based verification methodology to address the issues of
high demand of integrated circuit with the advanced features to
be delivered to market within tight Time-To-Market. The
concept of SystemVerilog Assertion (SVA) checker generator is
introduced to translate non-synthesizable verification coding
into hardware so-called assertion checker in Verilog. A lookup
table, which comprises of SVA operators mapped to their
corresponding synthesizable Verilog coding was developed to
generate assertion checker, which produces a single bit 1 when
the assertion fails. Collection module implemented using a
memory block and an arbiter was devised to be simple and fast
enough to collect assertion results from the assertion checker.
Since assertion checker can produce assertion result at any time,
an arbiter is required to act as an interface between assertion
checker and collection module. Case studies have been
conducted on the proof-of-concept designs, which are the first�in-first-out (FIFO), up-down counter and Context Adaptive
Variable Length Coding (CAVLC) to evaluate the effectiveness
of the proposed FPGA-assisted verification platform. In the case
studies, we have shown that the proposed FPGA-assisted
verification platform works correctly. Besides, we also evaluated
the method in area utilizations (ALMs). It has been proven that
simulation-based verification time can be reduced for as much
as 50% for complexity of VLSI design. Thus, implementing
assertions using hardware such as FPGA becomes a solution to
alleviate issue of long simulation time. |
| first_indexed | 2025-11-15T20:17:02Z |
| format | Article |
| id | uthm-6620 |
| institution | Universiti Tun Hussein Onn Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T20:17:02Z |
| publishDate | 2020 |
| publisher | Faculty of Electronic and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM) |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | uthm-66202022-03-10T03:33:49Z http://eprints.uthm.edu.my/6620/ FPGA-assisted assertion-based verification platform Mohamad, Nurita Chia, Yee Ooi Jwing Teh, Jwing Teh Paraman, Norlina Hassan, Hasliza Ismail, Nordinah TK7885-7895 Computer engineering. Computer hardware In this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the first�in-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time. Faculty of Electronic and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka (UTeM) 2020 Article PeerReviewed text en http://eprints.uthm.edu.my/6620/1/J13927_a4acd108d79f171fe2520f39b74e7a1e.pdf Mohamad, Nurita and Chia, Yee Ooi and Jwing Teh, Jwing Teh and Paraman, Norlina and Hassan, Hasliza and Ismail, Nordinah (2020) FPGA-assisted assertion-based verification platform. Journal of Telecommunication, Electronic and Computer Engineering, 12 (1). pp. 15-24. ISSN 2289-8131 |
| spellingShingle | TK7885-7895 Computer engineering. Computer hardware Mohamad, Nurita Chia, Yee Ooi Jwing Teh, Jwing Teh Paraman, Norlina Hassan, Hasliza Ismail, Nordinah FPGA-assisted assertion-based verification platform |
| title | FPGA-assisted assertion-based verification platform |
| title_full | FPGA-assisted assertion-based verification platform |
| title_fullStr | FPGA-assisted assertion-based verification platform |
| title_full_unstemmed | FPGA-assisted assertion-based verification platform |
| title_short | FPGA-assisted assertion-based verification platform |
| title_sort | fpga-assisted assertion-based verification platform |
| topic | TK7885-7895 Computer engineering. Computer hardware |
| url | http://eprints.uthm.edu.my/6620/ http://eprints.uthm.edu.my/6620/1/J13927_a4acd108d79f171fe2520f39b74e7a1e.pdf |