Low power 130 nm CMOS Johnson Counter with clock gating technique

Low power 130 nm CMOS Johnson Counter with clock gating technique

In a very large scale integration (VLSI) of integrated circuit (IC) nowadays, digital circuit with low power design is the target of the IC designer. This is to prolong the battery life of the circuit especially if it is meant for wearable devices. In most of the digital circuits, counters are used...

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Bibliographic Details
Main Authors: Amran, Nur Syuhadah, Ruslan, Siti Hawa
Format: Article
Language:English
Published: IOP Publishing 2018
Subjects:
TK5101-6720 Telecommunication. Including telegraphy, telephone, radio, radar, television
Online Access:http://eprints.uthm.edu.my/2902/
http://eprints.uthm.edu.my/2902/1/AJ%202019%20%2865%29.pdf

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