Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration.
| Main Author: | |
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| Format: | Final Year Project / Dissertation / Thesis |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://eprints.utar.edu.my/947/ http://eprints.utar.edu.my/947/1/CT%2D2013%2D904385%2D1.pdf |
| _version_ | 1848885353671294976 |
|---|---|
| author | Kim, Yuh Chang |
| author_facet | Kim, Yuh Chang |
| author_sort | Kim, Yuh Chang |
| building | UTAR Institutional Repository |
| collection | Online Access |
| first_indexed | 2025-11-15T19:21:15Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-947 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:21:15Z |
| publishDate | 2013 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-9472013-09-12T04:34:44Z Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. Kim, Yuh Chang TK Electrical engineering. Electronics Nuclear engineering 2013-01 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/947/1/CT%2D2013%2D904385%2D1.pdf Kim, Yuh Chang (2013) Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. Final Year Project, UTAR. http://eprints.utar.edu.my/947/ |
| spellingShingle | TK Electrical engineering. Electronics Nuclear engineering Kim, Yuh Chang Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. |
| title | Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. |
| title_full | Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. |
| title_fullStr | Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. |
| title_full_unstemmed | Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. |
| title_short | Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration. |
| title_sort | design and development of memory system for 32 bits 5-stage pipelined processor: main memory (dram) integration. |
| topic | TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utar.edu.my/947/ http://eprints.utar.edu.my/947/1/CT%2D2013%2D904385%2D1.pdf |