APA (7th ed.) Citation

Kim, Y. C. (2013). Design and development of memory system for 32 bits 5-stage pipelined processor: Main memory (DRAM) integration.

Chicago Style (17th ed.) Citation

Kim, Yuh Chang. Design and Development of Memory System for 32 Bits 5-stage Pipelined Processor: Main Memory (DRAM) Integration. 2013.

MLA (9th ed.) Citation

Kim, Yuh Chang. Design and Development of Memory System for 32 Bits 5-stage Pipelined Processor: Main Memory (DRAM) Integration. 2013.

Warning: These citations may not always be 100% accurate.