Efficient implementation of lattice-based cryptographic schemes for internet of things applications - Wong, Zheng Yan (2022)

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Lattice-based cryptography (LBC) is one of the most widely studied post-quantum cryptography (PQC) candidates to date. Polynomial multiplication (PM) and generation of error samples are two main bottlenecks in LBC. PM can be implemented through schoolbook polynomial multiplication algorithm (SPMA) and Number Theoretic Transform (NTT).The SPMA has always been the simplest form of performing PM, and often can be implemented through very light weight designs, but it suffers from low throughputs. NTT on the other hand, requires vast hardware utilization to cope with the high parallelism of the multiplication process,although capable of completing the PM process in a much shorter timeframe.Moreover, NTT requires special ring structure to operate, which may not be found in all LBC schemes. Karatsuba algorithm, being another candidate between these two extremes, are not widely studied for LBC scheme implementation in FPGA.Karatsuba algorithm can be used to speed up the PM process, while keeping the hardware utilization moderately lightweight. This fills in the gap between SPMA and NTT, creating a robust and packed polynomial multiplier, especially for IoT applications that requires higher security with hardware constraints.The main focus of this work is to develop a high-speed hardware architecture to improve the performance of PM in LBC schemes such as Ring Learning-with Error (R-LWE) and Learning-with-Errors (LWR) (Saber). This research work implemented a 1-layer Karatsuba architecture to improve the throughput of PM for R-LWE, and a 4-layer Karatsuba architecture to improve the throughput of PM for SABER. By breaking the polynomials into smaller sub-polynomials for multiplication, along with efficient data scheduling specifically for the Karatsuba algorithm, the throughput of PM is improved drastically.Furthermore, multiplicands are also stacked up to double the throughput in both R-LWE and SABER implementations. Last but not least, the negacyclic operations are integrated into the post-processing of Karatsuba, saving additional memory elements for storing the intermediate results, and reducing the time consume for computing the PM results.Experimental results show a speed up of 2.09× in throughput along with a 6.52% improvement in throughput-per-slice for the R-LWE polynomial multiplier. For the Saber polynomial multiplier, experimental results show a speed up of 2.17× in throughput along with a 73.55% improvement in throughput-per-slice.IoT applications require the sensor nodes to transmit sensor data frequently to the nearby gateway device. This implies that the implementation of public key scheme used in protecting such communication must achieve sufficient throughput in order to ensure a timely response. The proposed Karatsuba-based architecture allows high throughput performance, at the same time do not consume extremely large hardware area; this shows great potential to be used in IoT applications