Design and simulate RISC-V processor using verilog
In this project, RISC-V processor is designed and simulated using Verilog. The design of RISC-V processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISC-V processor will be...
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| Format: | Final Year Project / Dissertation / Thesis |
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2023
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| Online Access: | http://eprints.utar.edu.my/5966/ http://eprints.utar.edu.my/5966/1/David_Ngu_Teck_Joung_21AGM06719.pdf |
| _version_ | 1848886550859874304 |
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| author | Ngu, David Teck Joung |
| author_facet | Ngu, David Teck Joung |
| author_sort | Ngu, David Teck Joung |
| building | UTAR Institutional Repository |
| collection | Online Access |
| description | In this project, RISC-V processor is designed and simulated using Verilog. The design of RISC-V processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISC-V processor will be using 5- stage pipeline techniques to improve the overall performance of the processor. The project is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA and forwardMuxB. Besides, hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using ModelSim software. Then, the modules were integrated into a main module to form a riscv_pip_27 module. A simple testbench is written to verify the functionality of the RISC-V processor. |
| first_indexed | 2025-11-15T19:40:17Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-5966 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:40:17Z |
| publishDate | 2023 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-59662024-01-01T12:58:30Z Design and simulate RISC-V processor using verilog Ngu, David Teck Joung T Technology (General) TK Electrical engineering. Electronics Nuclear engineering In this project, RISC-V processor is designed and simulated using Verilog. The design of RISC-V processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISC-V processor will be using 5- stage pipeline techniques to improve the overall performance of the processor. The project is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA and forwardMuxB. Besides, hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using ModelSim software. Then, the modules were integrated into a main module to form a riscv_pip_27 module. A simple testbench is written to verify the functionality of the RISC-V processor. 2023-05 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/5966/1/David_Ngu_Teck_Joung_21AGM06719.pdf Ngu, David Teck Joung (2023) Design and simulate RISC-V processor using verilog. Master dissertation/thesis, UTAR. http://eprints.utar.edu.my/5966/ |
| spellingShingle | T Technology (General) TK Electrical engineering. Electronics Nuclear engineering Ngu, David Teck Joung Design and simulate RISC-V processor using verilog |
| title | Design and simulate RISC-V processor using verilog
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| title_full | Design and simulate RISC-V processor using verilog
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| title_fullStr | Design and simulate RISC-V processor using verilog
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| title_full_unstemmed | Design and simulate RISC-V processor using verilog
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| title_short | Design and simulate RISC-V processor using verilog
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| title_sort | design and simulate risc-v processor using verilog |
| topic | T Technology (General) TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utar.edu.my/5966/ http://eprints.utar.edu.my/5966/1/David_Ngu_Teck_Joung_21AGM06719.pdf |