Investigation of a 3 nm Strained Fin Field-Effect Transistor (FinFET) - Tan, Pei Xin (2023)

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Fin Field-Effect Transistor (FinFET) device is qualified for its low-power operation capability at which the performance can be improved with further scaling. However, critical scaling towards 10nm of FinFET leads to a series of issues such as drain-induced barrier lowering (DIBL), threshold voltage roll-off, hot carrier effects, reverse leakage current rise which affecting the functionality of the device. Shrinking of MOSFET transistor size is no longer sufficient to boost integrated circuit performance for higher generation of technology. To address this issue, the design of 3nm strained FinFET using strained SiGe wafer is proposed. In this project. 3nm FinFET is implemented using GMSH software and 3D-DDCC software. Simulation is performed using 3D-DDCC simulator to investigate the respective performance as compared with conventional Si FinFET. Both designs conform with the standard characteristics of an operational FinFET. By analysing both the output and transfer characteristic of both FinFET design, the drive current of strained FinFET is proven to be higher than conventional FinFET which indicating higher performance. Besides, the current leakage of SiGe FinFET is identified to be higher than Si FinFET by 17.19% due to enhanced electron mobility. Even so, the leakage current is found to be low in 0.075 μA which causes negligible effect in power consumption and temperature dissipation. Further study can be done to investigate the possibility of leakage current reduction using triangular shaped FinFET, GAAFET structure and high-k dielectric material for the benefit of variety of people.