Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler

This research paper focuses on the development of an Automatic Place and Route (APR) methodology for the RISC-V processor design using the IC Compiler tool. The proposed methodology is aimed at achieving good Quality of Results (QoR) for different technology nodes, including 32nm and 90nm. The paper...

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Main Author: Loh, Jing En
Format: Final Year Project / Dissertation / Thesis
Published: 2023
Subjects:
Online Access:http://eprints.utar.edu.my/5959/
http://eprints.utar.edu.my/5959/1/Loh_Jing_En_21AGM06712.pdf
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author Loh, Jing En
author_facet Loh, Jing En
author_sort Loh, Jing En
building UTAR Institutional Repository
collection Online Access
description This research paper focuses on the development of an Automatic Place and Route (APR) methodology for the RISC-V processor design using the IC Compiler tool. The proposed methodology is aimed at achieving good Quality of Results (QoR) for different technology nodes, including 32nm and 90nm. The paper provides a detailed analysis of the QoR obtained for each technology node and compares the results obtained with each other. On top of that, the effect of clock period on the design quality is also analyzed. The methodology used for the design flow and the physical implementation process of the design using IC Compiler are all explained in detail. The experimental results demonstrate the effectiveness of the proposed methodology in achieving good QoR for RISC-V processor designs.
first_indexed 2025-11-15T19:40:15Z
format Final Year Project / Dissertation / Thesis
id utar-5959
institution Universiti Tunku Abdul Rahman
institution_category Local University
last_indexed 2025-11-15T19:40:15Z
publishDate 2023
recordtype eprints
repository_type Digital Repository
spelling utar-59592024-01-01T12:47:30Z Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler Loh, Jing En T Technology (General) TK Electrical engineering. Electronics Nuclear engineering This research paper focuses on the development of an Automatic Place and Route (APR) methodology for the RISC-V processor design using the IC Compiler tool. The proposed methodology is aimed at achieving good Quality of Results (QoR) for different technology nodes, including 32nm and 90nm. The paper provides a detailed analysis of the QoR obtained for each technology node and compares the results obtained with each other. On top of that, the effect of clock period on the design quality is also analyzed. The methodology used for the design flow and the physical implementation process of the design using IC Compiler are all explained in detail. The experimental results demonstrate the effectiveness of the proposed methodology in achieving good QoR for RISC-V processor designs. 2023-05 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/5959/1/Loh_Jing_En_21AGM06712.pdf Loh, Jing En (2023) Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler. Master dissertation/thesis, UTAR. http://eprints.utar.edu.my/5959/
spellingShingle T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
Loh, Jing En
Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler
title Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler
title_full Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler
title_fullStr Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler
title_full_unstemmed Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler
title_short Back End Design (Automatic Place and Route) of RISC-V Processor using IC Compiler
title_sort back end design (automatic place and route) of risc-v processor using ic compiler
topic T Technology (General)
TK Electrical engineering. Electronics Nuclear engineering
url http://eprints.utar.edu.my/5959/
http://eprints.utar.edu.my/5959/1/Loh_Jing_En_21AGM06712.pdf