Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench

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Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench

MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and...

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Bibliographic Details
Main Author:	Teng, Wen Jun
Format:	Final Year Project / Dissertation / Thesis
Published:	2023
Subjects:	S Agriculture (General) TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utar.edu.my/5957/ http://eprints.utar.edu.my/5957/1/Teng_Wen_Jun_21AGM06710.pdf

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