Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and...
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| Format: | Final Year Project / Dissertation / Thesis |
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2023
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| Online Access: | http://eprints.utar.edu.my/5957/ http://eprints.utar.edu.my/5957/1/Teng_Wen_Jun_21AGM06710.pdf |
| _version_ | 1848886548434518016 |
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| author | Teng, Wen Jun |
| author_facet | Teng, Wen Jun |
| author_sort | Teng, Wen Jun |
| building | UTAR Institutional Repository |
| collection | Online Access |
| description | MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and validating the correctness of the processor if a complex work as it consists of about 111 total instructions (Stanford.edu, 2020). Various types of hazards might be arise due to the complexity of the pipeline structures. Thus, the verification process will be time consuming as validators need to verify the whole design by checking the waveforms after they make some minor changes. This project is to improve the efficiency of verification process of the current RISC32 5-stage pipeline processor that developed in Universiti Tunku Abdul Rahman which is under Faculty of Information Technology by developing a complete self-checking testbench using SystemVerilog to verify the functional correctness of the MIPS design at system level. |
| first_indexed | 2025-11-15T19:40:15Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-5957 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:40:15Z |
| publishDate | 2023 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-59572024-01-01T12:42:51Z Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench Teng, Wen Jun S Agriculture (General) TK Electrical engineering. Electronics Nuclear engineering MIPS stand for Microprocessor without Interlocked Pipeline Stages. It is a reduced instruction set computer (RISC) instruction set architecture (ISA). RISC is a wellstablished architecture due to its efficiency and simplicity. Thus, it is widely used in the processor industry. However, verifying and validating the correctness of the processor if a complex work as it consists of about 111 total instructions (Stanford.edu, 2020). Various types of hazards might be arise due to the complexity of the pipeline structures. Thus, the verification process will be time consuming as validators need to verify the whole design by checking the waveforms after they make some minor changes. This project is to improve the efficiency of verification process of the current RISC32 5-stage pipeline processor that developed in Universiti Tunku Abdul Rahman which is under Faculty of Information Technology by developing a complete self-checking testbench using SystemVerilog to verify the functional correctness of the MIPS design at system level. 2023-05 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/5957/1/Teng_Wen_Jun_21AGM06710.pdf Teng, Wen Jun (2023) Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench. Master dissertation/thesis, UTAR. http://eprints.utar.edu.my/5957/ |
| spellingShingle | S Agriculture (General) TK Electrical engineering. Electronics Nuclear engineering Teng, Wen Jun Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench |
| title | Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
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| title_full | Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
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| title_fullStr | Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
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| title_full_unstemmed | Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
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| title_short | Verification of Microprocessor without Interlocked Pipeline (MIPS) Processor using Self-Checking Testbench
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| title_sort | verification of microprocessor without interlocked pipeline (mips) processor using self-checking testbench |
| topic | S Agriculture (General) TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utar.edu.my/5957/ http://eprints.utar.edu.my/5957/1/Teng_Wen_Jun_21AGM06710.pdf |