Verification of RISC-V design with Universal Verification Methodology (UVM)

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Verification of RISC-V design with Universal Verification Methodology (UVM)

Throughout the design life cycle of a processor, verification plays a crucial part in affirming the functionalities of the features implemented based on the computer architecture used. Functional verification increases the level of confidence in conformance of the processor design to its specificati...

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Bibliographic Details
Main Author:	Liew, You Hong
Format:	Final Year Project / Dissertation / Thesis
Published:	2022
Subjects:	T Technology (General) TK Electrical engineering. Electronics Nuclear engineering
Online Access:	http://eprints.utar.edu.my/4903/ http://eprints.utar.edu.my/4903/1/fyp_EE_LYH_2022.pdf

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