Verification of RISC-V design with Universal Verification Methodology (UVM) - Liew, You Hong (2022)

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Throughout the design life cycle of a processor, verification plays a crucial part in affirming the functionalities of the features implemented based on the computer architecture used. Functional verification increases the level of confidence in conformance of the processor design to its specification. In the case of a processor with advanced microarchitectural features implemented, a simulation-based approach is taken for its functional verification. More specifically, Universal Verification Methodology (UVM) is utilized for the verification methodology of the RISC-V processor implementation in this report. UVM provides a set of guidelines for the verification testbenches to be generated. With a well-defined testbench structure, UVM allows for a standardized approach towards verification works and verifications of systems to be performed consistently and uniformly, greatly improving verification quality and reusability of testbenches. For the verification approach, constrained random verification and direct verification approaches will be taken to verify the functionality of the RISC-V processor. In the verification methodology, results validation has been utilized whereby the output data of the simulation model is compared with comparable output data from an existing system. For verification purpose, a reference model is developed and will be utilized for the results validation methodology mentioned. On verification simulations, discrepancies between the output data from the simulation models and the reference model are identified as design bugs in the system and debugs will be performed to fix the design bugs in the system. Through numerous test runs on the RISC-V processor implementation, the bugs on the RTL design of the processor designed are reduced to a minimum and the processor can function as specified by the computer architecture