Design of a 7-Stage pipeline RISC processor (MEM STAGE)
This project is about the design and implementation of a 32-bits RISC 7-Stage pipeline processor for academic purpose. The main objective of this project is to improve the performance of the existing 32-bits RISC 5-stage pipeline processor developed in Faculty of Information, Communication and Techn...
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| Format: | Final Year Project / Dissertation / Thesis |
| Published: |
2022
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| Online Access: | http://eprints.utar.edu.my/4625/ http://eprints.utar.edu.my/4625/1/fyp_CT_2022_CJZ.pdf |
| _version_ | 1848886199981178880 |
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| author | Choo, Jia Zheng |
| author_facet | Choo, Jia Zheng |
| author_sort | Choo, Jia Zheng |
| building | UTAR Institutional Repository |
| collection | Online Access |
| description | This project is about the design and implementation of a 32-bits RISC 7-Stage pipeline processor for academic purpose. The main objective of this project is to improve the performance of the existing 32-bits RISC 5-stage pipeline processor developed in Faculty of Information, Communication and Technology, University Tunku Abdul Rahman. The performance of the processor is improved and optimized by increasing the number of pipeline stages to obtain a shorter time delay for each stage. The MEM stages of the existing pipeline processor contribute to the longest timing delay, which reduce the performance of the processor due to the imbalance logics among the stages. In this project, the data cache unit is decomposed and pipelined into 2 stages. Cache unit access will now require two clock cycle if a CACHE HIT is detected. Another extra stage is reserved for the implementation of Translation Look Aside Buffer (TLB) in the future. Some modifications on the cache controller is done to improve its performance too. The newly developed data cache unit is modelled using Verilog coding follow with its functional verification. Lastly, synthesis and implementation using Xilinx Vivado is done to obtain the timing delay of the new developed 7-stage RISC pipeline processor. |
| first_indexed | 2025-11-15T19:34:42Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-4625 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:34:42Z |
| publishDate | 2022 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-46252023-01-15T13:18:21Z Design of a 7-Stage pipeline RISC processor (MEM STAGE) Choo, Jia Zheng TA Engineering (General). Civil engineering (General) TF Railroad engineering and operation TG Bridge engineering TK Electrical engineering. Electronics Nuclear engineering This project is about the design and implementation of a 32-bits RISC 7-Stage pipeline processor for academic purpose. The main objective of this project is to improve the performance of the existing 32-bits RISC 5-stage pipeline processor developed in Faculty of Information, Communication and Technology, University Tunku Abdul Rahman. The performance of the processor is improved and optimized by increasing the number of pipeline stages to obtain a shorter time delay for each stage. The MEM stages of the existing pipeline processor contribute to the longest timing delay, which reduce the performance of the processor due to the imbalance logics among the stages. In this project, the data cache unit is decomposed and pipelined into 2 stages. Cache unit access will now require two clock cycle if a CACHE HIT is detected. Another extra stage is reserved for the implementation of Translation Look Aside Buffer (TLB) in the future. Some modifications on the cache controller is done to improve its performance too. The newly developed data cache unit is modelled using Verilog coding follow with its functional verification. Lastly, synthesis and implementation using Xilinx Vivado is done to obtain the timing delay of the new developed 7-stage RISC pipeline processor. 2022-04-18 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/4625/1/fyp_CT_2022_CJZ.pdf Choo, Jia Zheng (2022) Design of a 7-Stage pipeline RISC processor (MEM STAGE). Final Year Project, UTAR. http://eprints.utar.edu.my/4625/ |
| spellingShingle | TA Engineering (General). Civil engineering (General) TF Railroad engineering and operation TG Bridge engineering TK Electrical engineering. Electronics Nuclear engineering Choo, Jia Zheng Design of a 7-Stage pipeline RISC processor (MEM STAGE) |
| title | Design of a 7-Stage pipeline RISC processor
(MEM STAGE) |
| title_full | Design of a 7-Stage pipeline RISC processor
(MEM STAGE) |
| title_fullStr | Design of a 7-Stage pipeline RISC processor
(MEM STAGE) |
| title_full_unstemmed | Design of a 7-Stage pipeline RISC processor
(MEM STAGE) |
| title_short | Design of a 7-Stage pipeline RISC processor
(MEM STAGE) |
| title_sort | design of a 7-stage pipeline risc processor
(mem stage) |
| topic | TA Engineering (General). Civil engineering (General) TF Railroad engineering and operation TG Bridge engineering TK Electrical engineering. Electronics Nuclear engineering |
| url | http://eprints.utar.edu.my/4625/ http://eprints.utar.edu.my/4625/1/fyp_CT_2022_CJZ.pdf |