The Design of an Asynchronous RISC Processor - Pee, Yao Hong (2021)
This project is an asynchronous processor design project for academic purpose. It will provide students with the methodology, concept and design of asynchronous RISC processor. This will be illustrated by converting a synchronous processor to an asynchronous processor. This can be done by substituting the global clock for a synchronous processor with a set of controllers that all have an equivalent behavior. Since asynchronous processor is better than synchronous processor in aspects of no clock skew, lower power dissipation and etc, it is well suited for digital circuits and therefore implemented in this project. The tools used in this project are Verilog hardware description language in combination with ModelSim synthesis tools and PCSpim. Moreover, there is several types of asynchronous implementation style and the one used here is the 4-phase single-rail pipeline. The verification plan of the project is a testbench with numbers of instruction to make sure the processor is workable. Lastly, the output of the project would be the synthesized hardware of asynchronous RISC processor with shortest delay for every single instruction in order to implement that asynchronous processor is better than synchronous processor.