Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture
| Main Author: | |
|---|---|
| Format: | Final Year Project / Dissertation / Thesis |
| Published: |
2018
|
| Online Access: | http://eprints.utar.edu.my/2954/ http://eprints.utar.edu.my/2954/1/ESA%2D2018%2D1600306%2D1.pdf |
| _version_ | 1848885788737011712 |
|---|---|
| author | Chong, Sin Ran |
| author_facet | Chong, Sin Ran |
| author_sort | Chong, Sin Ran |
| building | UTAR Institutional Repository |
| collection | Online Access |
| first_indexed | 2025-11-15T19:28:10Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-2954 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:28:10Z |
| publishDate | 2018 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-29542019-03-21T18:17:57Z Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture Chong, Sin Ran 2018-04 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/2954/1/ESA%2D2018%2D1600306%2D1.pdf Chong, Sin Ran (2018) Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture. Master dissertation/thesis, UTAR. http://eprints.utar.edu.my/2954/ |
| spellingShingle | Chong, Sin Ran Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture |
| title | Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture |
| title_full | Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture |
| title_fullStr | Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture |
| title_full_unstemmed | Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture |
| title_short | Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture |
| title_sort | studies to improve the process of decoding rateless erasure code with highly-parallel gpu architecture |
| url | http://eprints.utar.edu.my/2954/ http://eprints.utar.edu.my/2954/1/ESA%2D2018%2D1600306%2D1.pdf |