APA (7th ed.) Citation

Chong, S. R. (2018). Studies to improve the process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture.

Chicago Style (17th ed.) Citation

Chong, Sin Ran. Studies to Improve the Process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture. 2018.

MLA (9th ed.) Citation

Chong, Sin Ran. Studies to Improve the Process of Decoding Rateless Erasure Code with Highly-Parallel GPU Architecture. 2018.

Warning: These citations may not always be 100% accurate.