APA (7th ed.) Citation

Goh, D. J. (2015). Design and Development of Memory System for 32-bit 5 Stage Pipeline RISC: Memory System Integration.

Chicago Style (17th ed.) Citation

Goh, Dih Jiann. Design and Development of Memory System for 32-bit 5 Stage Pipeline RISC: Memory System Integration. 2015.

MLA (9th ed.) Citation

Goh, Dih Jiann. Design and Development of Memory System for 32-bit 5 Stage Pipeline RISC: Memory System Integration. 2015.

Warning: These citations may not always be 100% accurate.