APA (7th ed.) Citation

Chang, B. C. (2015). 32-bit 5-stage RISC pipeline processor with 2-Bit dynamic branch prediction functionality.

Chicago Style (17th ed.) Citation

Chang, Boon Chiao. 32-bit 5-stage RISC Pipeline Processor with 2-Bit Dynamic Branch Prediction Functionality. 2015.

MLA (9th ed.) Citation

Chang, Boon Chiao. 32-bit 5-stage RISC Pipeline Processor with 2-Bit Dynamic Branch Prediction Functionality. 2015.