Ho, M. C. (2013). The design and development of a branch target buffer based on a 2-bit prediction scheme for a 32-bit RISC32 pipeline processor.
Chicago Style (17th ed.) CitationHo, Ming Cheng. The Design and Development of a Branch Target Buffer Based on a 2-bit Prediction Scheme for a 32-bit RISC32 Pipeline Processor. 2013.
MLA (9th ed.) CitationHo, Ming Cheng. The Design and Development of a Branch Target Buffer Based on a 2-bit Prediction Scheme for a 32-bit RISC32 Pipeline Processor. 2013.
Warning: These citations may not always be 100% accurate.