Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM
| Main Author: | |
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| Format: | Final Year Project / Dissertation / Thesis |
| Published: |
2013
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| Subjects: | |
| Online Access: | http://eprints.utar.edu.my/1175/ http://eprints.utar.edu.my/1175/1/CT%2D2013%2D1002389%2D1.pdf |
| _version_ | 1848885392521035776 |
|---|---|
| author | Ching, Li-Lynn |
| author_facet | Ching, Li-Lynn |
| author_sort | Ching, Li-Lynn |
| building | UTAR Institutional Repository |
| collection | Online Access |
| first_indexed | 2025-11-15T19:21:52Z |
| format | Final Year Project / Dissertation / Thesis |
| id | utar-1175 |
| institution | Universiti Tunku Abdul Rahman |
| institution_category | Local University |
| last_indexed | 2025-11-15T19:21:52Z |
| publishDate | 2013 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | utar-11752014-07-03T03:36:34Z Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM Ching, Li-Lynn T Technology (General) 2013-08-30 Final Year Project / Dissertation / Thesis NonPeerReviewed application/pdf http://eprints.utar.edu.my/1175/1/CT%2D2013%2D1002389%2D1.pdf Ching, Li-Lynn (2013) Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM. Final Year Project, UTAR. http://eprints.utar.edu.my/1175/ |
| spellingShingle | T Technology (General) Ching, Li-Lynn Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM |
| title | Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM |
| title_full | Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM |
| title_fullStr | Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM |
| title_full_unstemmed | Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM |
| title_short | Memory system design: Integration of caches, translation lookaside buffers (TLB) and SDRAM |
| title_sort | memory system design: integration of caches, translation lookaside buffers (tlb) and sdram |
| topic | T Technology (General) |
| url | http://eprints.utar.edu.my/1175/ http://eprints.utar.edu.my/1175/1/CT%2D2013%2D1002389%2D1.pdf |