Design Of Up-Conversion Mixer Using Silterra 0.18 mm Cmos Process Technology
This dissertation presents a design of up conversion mixer for Ultra Wideband (UWB) application using Silterra 0.18 µm CMOS process technology. The design includes study of the current UWB technology, RF transceiver system and in depth of the mixer. After gain some knowledge of the design matt...
| Main Author: | |
|---|---|
| Format: | Monograph |
| Language: | English |
| Published: |
Universiti Sains Malaysia
2006
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/58671/ http://eprints.usm.my/58671/1/Design%20Of%20Up-Conversion%20Mixer%20Using%20Silterra%200.18%20mm%20Cmos%20Process%20Technology_Mohd%20Zakaria%20Husin.pdf |
| Summary: | This dissertation presents a design of up conversion mixer for Ultra Wideband
(UWB) application using Silterra 0.18 µm CMOS process technology. The design includes
study of the current UWB technology, RF transceiver system and in depth of the mixer.
After gain some knowledge of the design matters, the design of the real circuit is taken
placed. The mixer that is going to be design is based on active double balanced Gilbert type
topology. This type topology is chosen among the others topology (i.e. single balanced)
because it have better performance in terms of gain, intermodulation, port-to-port isolation
and the suppression of local oscillator (LO) signal. A large LO signal at the RF output port
typically leads to very poor mixer intermodulation performance and can also cause
compression in the first RF amplifier. A double balanced mixer structure provides not only
fully differential, but also a virtual ground for the LO signal at the output RF port, and no
special active or passive circuitry is required to provide this LO short. In this design, new
technique to improve linearity and performance of the mixer was introduced. Current
bleeding technique using PMOS was utilized in the design in order to improve the linearity,
conversion gain and noise figure. The performance of this mixer is expected to have
conversion gain larger than 5 dB, 1dB compression larger than 5 dBm, input IP3 (IIP3)
larger than 10 dBm and consume power of 36 mW from 1.8 V supply voltage. Mixer will
multiply input signal IF which is frequency at 264 MHz with local oscillator (LO) signal
which is frequency at 3.96 GHz and hence produced the output RF signal which is at
frequency of 3.696 GHz. All simulation of the mixer is done by using Spectre from
Cadence design kit. |
|---|