Design Of An 8 Bit Receiver Based On FPGA
This project is developed in purpose to design and build a receiver in UART (Universal Asynchronous Receive Transmit) based on FPGA (Field Programmable Gate Array). There are two main parts associated in developing this receiver including software development and hardware installation. The most im...
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| Format: | Monograph |
| Language: | English |
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Universiti Sains Malaysia
2006
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| Online Access: | http://eprints.usm.my/58612/ http://eprints.usm.my/58612/1/Design%20Of%20An%208%20Bit%20Receiver%20Based%20On%20FPGA_Haidzir%20Mohammad_E3_2006_ESAR.pdf |
| _version_ | 1848883945282732032 |
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| author | Mohammad, Haidzir |
| author_facet | Mohammad, Haidzir |
| author_sort | Mohammad, Haidzir |
| building | USM Institutional Repository |
| collection | Online Access |
| description | This project is developed in purpose to design and build a receiver in UART (Universal Asynchronous Receive Transmit) based on FPGA (Field Programmable Gate Array). There are two main parts associated in developing this receiver including
software development and hardware installation. The most important part in this project is, in software development section where involving to develop the whole receiver application using Xilinx Foundation 2.1i software based on VHDL (Hardware Description Language) code via Behavioral Modelling. This receiver will have functionality as a receiver in UART to accept 8 bit data in serial and converted to 8 bit data in parallel for communication in computer system. For hardware installation part, it involve a whole connection circuitry with Xilinx XC4010PC84 demo board with computer via connection RS232 cable and the other hardware connection. The Xilinx
XC4010PC84 demo board will act like a receiver and display the data that computer send in ASCII character and display it by LED in binary. |
| first_indexed | 2025-11-15T18:58:52Z |
| format | Monograph |
| id | usm-58612 |
| institution | Universiti Sains Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T18:58:52Z |
| publishDate | 2006 |
| publisher | Universiti Sains Malaysia |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | usm-586122023-05-18T08:24:40Z http://eprints.usm.my/58612/ Design Of An 8 Bit Receiver Based On FPGA Mohammad, Haidzir T Technology TK Electrical Engineering. Electronics. Nuclear Engineering This project is developed in purpose to design and build a receiver in UART (Universal Asynchronous Receive Transmit) based on FPGA (Field Programmable Gate Array). There are two main parts associated in developing this receiver including software development and hardware installation. The most important part in this project is, in software development section where involving to develop the whole receiver application using Xilinx Foundation 2.1i software based on VHDL (Hardware Description Language) code via Behavioral Modelling. This receiver will have functionality as a receiver in UART to accept 8 bit data in serial and converted to 8 bit data in parallel for communication in computer system. For hardware installation part, it involve a whole connection circuitry with Xilinx XC4010PC84 demo board with computer via connection RS232 cable and the other hardware connection. The Xilinx XC4010PC84 demo board will act like a receiver and display the data that computer send in ASCII character and display it by LED in binary. Universiti Sains Malaysia 2006-05-01 Monograph NonPeerReviewed application/pdf en http://eprints.usm.my/58612/1/Design%20Of%20An%208%20Bit%20Receiver%20Based%20On%20FPGA_Haidzir%20Mohammad_E3_2006_ESAR.pdf Mohammad, Haidzir (2006) Design Of An 8 Bit Receiver Based On FPGA. Project Report. Universiti Sains Malaysia, Pusat Pengajian Kejuruteraan Elektrik dan Elektronik. (Submitted) |
| spellingShingle | T Technology TK Electrical Engineering. Electronics. Nuclear Engineering Mohammad, Haidzir Design Of An 8 Bit Receiver Based On FPGA |
| title | Design Of An 8 Bit Receiver Based On FPGA |
| title_full | Design Of An 8 Bit Receiver Based On FPGA |
| title_fullStr | Design Of An 8 Bit Receiver Based On FPGA |
| title_full_unstemmed | Design Of An 8 Bit Receiver Based On FPGA |
| title_short | Design Of An 8 Bit Receiver Based On FPGA |
| title_sort | design of an 8 bit receiver based on fpga |
| topic | T Technology TK Electrical Engineering. Electronics. Nuclear Engineering |
| url | http://eprints.usm.my/58612/ http://eprints.usm.my/58612/1/Design%20Of%20An%208%20Bit%20Receiver%20Based%20On%20FPGA_Haidzir%20Mohammad_E3_2006_ESAR.pdf |