Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM

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Design A High Performance Dual Ported 1 Read 1 Write CMOS SRAM

A synchronous dual-ported high speed and low power CMOS SRAM is described. This SRAM is an 8T (transistors) architecture that has 8 transistors in every single memory cell that are capable of performing a read and write operation in one cycle, under the condition that it is not performing the...

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Bibliographic Details
Main Author:	Yeoh, Ee Ee
Format:	Monograph
Language:	English
Published:	Universiti Sains Malaysia 2006
Subjects:	T Technology TK Electrical Engineering. Electronics. Nuclear Engineering
Online Access:	http://eprints.usm.my/58608/ http://eprints.usm.my/58608/1/Design%20A%20High%20Performance%20Dual%20Ported%201%20Read%201%20Write%20CMOS%20SRAM_Yeoh%20Ee%20Ee.pdf

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