Thermal Management In Stacked Dies - Norman, Hua Shijie (Universiti Sains Malaysia, 2005)
The present trend in integrated circuit (IC) packaging, geared towards reduction in size and higher functionality in IC packages, has called about the need for integrating dies vertically in a single package. Added functionality and capacity of stacked dies packages within the same footprint as a single die package practically means higher power densities packages, and this is where thermal issues arise. Through the present study, it is of utmost interest to determine how the temperature and stress distribution within the package varies with the different loads of power applied in the silicon dies. The findings from the present study are of in-depth meaning particularly in the thermal management aspect because the challenge arises in attempting to remove heat efficiently from stacked dies packages. The research study is facilitated with ANSYSTM 7.0, which is used as a finite element modelling and analysis tool. The temperature and stress distribution in stacked dies packages under different source power is studied. Thermal stresses are induced in the package as a result of mismatch in the coefficient of thermal expansion (CTE) properties of the various package materials. Warpage of the package is to be limited to avoid the loss of electrical and mechanical connections. For all cases, the junction temperature and stress increases linearly with total power generation rates in the package. The junction temperature in each package is found to be independent of the power splitting ratios among the dies. The increment in junction temperature with respect to total power decreases from the single die package to the four stacked dies package. The printed circuit board provides a conduction path for effective heat removal from the bottom of the package to ambient as proven from the simulation results.