Design Of 0.13-µm CMOS LNA With Flat Gain For Cognitive Radio Application - Roslan, Muhammad Asyraf (Universiti Sains Malaysia, 2018)
This thesis presents the design of a wide band low noise amplifier (LNA) with high gain for ultra-wideband (UWB) application ranging from 300 MHz to 10 GHz. In implementing the LNA design, the design must able to provide wide bandwidth with high flat gain while the performance metrics optimized to the target specifications. In this design project, the LNA utilizes the input transistor with the Common Gate (CG) topology to obtain wideband input cascaded with a transistor of Common Source (CS) topology for enhancement in gain and act as current amplifier to lower the power consumption. In a previous study, by using the proposed topology, a wideband LNA of 300 MHz to 10 GHz was obtained using ideal passive components. This work is a continuation of the above mention project, whereby the design is converted to using RF components. Cadence Spectre RF software with Silterra’s 0.13-µm CMOS process technology is used in simulation of the LNA design to present results of the performance metrics of the proposed LNA. The LNA with RF components achieved gain above 10 dB for the range of 2.4 GHz – 9.2 GHz, S11 -10 dB (2.5 GHz - 8.7 GHz), S12 below -40 dB, S22 below -10 dB and noise figure (NF) is between 5.4-7.2 dB (3 GHz – 7.2 GHz) with IP3dB of -6.47 dBm. The power consumption is 10.1 mW at 1.2 V. As for the RF optimized for 300 MHz -10 GHz, the gain was only achievable at the range of 1.193 GHz - 3.847 GHz, however the other performance metrics shows good result, S11 -10 dB (732 MHz - 8.03 GHz), S12 below -50 dB for the whole 300 MHz to 10 GHz, S22-10 dB (476 MHz - 9.82 GHz). The power consumption is 8.3 mW at 1.2 V. Based on the results of the optimised circuit, it can be seen that the first circuit with RF components gives better performance for 3 GHz – 10 GHz operation.