Effective Resistivity Analysis Using Cpw Transmission Line Model For Au-Compensated High Resistivity Silicon Substrate - Wong, Soo Theng (Universiti Sains Malaysia, 2017)
The rapid development of wireless communication has led to the need for high-speed electronic device. The current integrated complementary metal oxide semiconductor (CMOS) suffer from high energy losses and this factor can be eliminated using high resistivity silicon substrate. However, the drawback of using high resistivity silicon substrate is the presence of free carrier charges at oxide-silicon interface due to the parasitic surface conduction. Though deep level doping compensation using gold has shown a potential of suppressing the parasitic surface conduction effect and providing a high resistivity to the silicon substrate, there are no solid evidence to support this method. Thus, the goal of this project is to quantify the potential of Au-compensated high resistivity silicon substrate in suppressing the parasitic surface conduction. The attenuation losses of the Coplanar Waveguide Transmission Line on the substrate is firstly measured using the extracted S-parameter data. The figure of merit technique using effective resistivity characterisation is then used to analyse and quantify the capability of the substrate. The outcomes of the numerical analysis had shown a constant value of effective resistivity for Au-compensated high resistivity silicon substrate thus justifying the potential of Au-compensated high resistivity silicon substrate in suppressing the parasitic surface conduction as it shows bias-independent results when bias voltage is applied to the device.