Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality

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Clock Gating Assertion Check An Approach Towards Efficient Verification Closure On Clock Gating Functionality

One of the power reduction techniques widely used in Register Transfer Level (RTL) stage of a design is clock gating. However, the addition of clock gating logics has increased the complexity of a design and therefore considerable amount of verification effort is required. The conventional verificat...

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Bibliographic Details
Main Author:	Wang, Jian Zhong
Format:	Thesis
Language:	English
Published:	2017
Subjects:	T Technology TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Online Access:	http://eprints.usm.my/46474/ http://eprints.usm.my/46474/1/Clock%20Gating%20Assertion%20Check%20An%20Approach%20Towards%20Efficient%20Verification%20Closure%20On%20Clock%20Gating%20Functionality.pdf

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