Accelerated Verilog Simulator Using Application Specific Microprocessor
Logic simulation is an important step in Very Large Scale Integration (VLSI) IC development. Advancement in Hardware Description Language (HDL) has made Verilog a widely adopted language used to model digital circuit and verification test bench. Electronic Design Automation (EDA) vendor provides...
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| Format: | Thesis |
| Language: | English |
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2017
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| Online Access: | http://eprints.usm.my/45788/ http://eprints.usm.my/45788/1/Accelerated%20Verilog%20Simulator%20Using%20Application%20Specific%20Microprocessor.pdf |
| _version_ | 1848880426303619072 |
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| author | Tan Tze Sin, Tze Sin |
| author_facet | Tan Tze Sin, Tze Sin |
| author_sort | Tan Tze Sin, Tze Sin |
| building | USM Institutional Repository |
| collection | Online Access |
| description | Logic simulation is an important step in Very Large Scale Integration (VLSI)
IC development. Advancement in Hardware Description Language (HDL) has made
Verilog a widely adopted language used to model digital circuit and verification test
bench. Electronic Design Automation (EDA) vendor provides software and hardwareassisted
approaches to carry out simulations. However, software-based simulator is
slow whereas hardware-assisted simulator does not offer the same simulation fidelity
stipulated in Verilog. In this research project, a hardware-assisted Verilog simulator,
VerCPU System, was proposed to address shortcomings in existing platforms. The
simulator core is a custom designed application specific microprocessor specifically
adapted to handle Verilog simulation. The microprocessor computes Verilog data in
its native form while supporting event-driven parallelism directly to achieve speed
supremacy. Being a compiled-code simulator, simulation fidelity compliancy is
retained to offer the same result and visibility like the software-based solution. A
functional system, VerCPU, was developed and prototyped on a Field Programmable
Gate Array (FPGA) development board. This system was successfully verified and
benchmarked against a software-based compiled-code simulator, i.e. Synopsys VCS®.
VerCPU System can already achieve up to 6 times speed superiority with basic speed
improvement techniques applied. The simulator had proven to be a viable alternate
Verilog simulator to meet future simulation needs. |
| first_indexed | 2025-11-15T18:02:56Z |
| format | Thesis |
| id | usm-45788 |
| institution | Universiti Sains Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T18:02:56Z |
| publishDate | 2017 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | usm-457882021-11-17T03:42:16Z http://eprints.usm.my/45788/ Accelerated Verilog Simulator Using Application Specific Microprocessor Tan Tze Sin, Tze Sin T Technology TK Electrical Engineering. Electronics. Nuclear Engineering Logic simulation is an important step in Very Large Scale Integration (VLSI) IC development. Advancement in Hardware Description Language (HDL) has made Verilog a widely adopted language used to model digital circuit and verification test bench. Electronic Design Automation (EDA) vendor provides software and hardwareassisted approaches to carry out simulations. However, software-based simulator is slow whereas hardware-assisted simulator does not offer the same simulation fidelity stipulated in Verilog. In this research project, a hardware-assisted Verilog simulator, VerCPU System, was proposed to address shortcomings in existing platforms. The simulator core is a custom designed application specific microprocessor specifically adapted to handle Verilog simulation. The microprocessor computes Verilog data in its native form while supporting event-driven parallelism directly to achieve speed supremacy. Being a compiled-code simulator, simulation fidelity compliancy is retained to offer the same result and visibility like the software-based solution. A functional system, VerCPU, was developed and prototyped on a Field Programmable Gate Array (FPGA) development board. This system was successfully verified and benchmarked against a software-based compiled-code simulator, i.e. Synopsys VCS®. VerCPU System can already achieve up to 6 times speed superiority with basic speed improvement techniques applied. The simulator had proven to be a viable alternate Verilog simulator to meet future simulation needs. 2017-05 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/45788/1/Accelerated%20Verilog%20Simulator%20Using%20Application%20Specific%20Microprocessor.pdf Tan Tze Sin, Tze Sin (2017) Accelerated Verilog Simulator Using Application Specific Microprocessor. PhD thesis, Universiti Sains Malaysia. |
| spellingShingle | T Technology TK Electrical Engineering. Electronics. Nuclear Engineering Tan Tze Sin, Tze Sin Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title | Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_full | Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_fullStr | Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_full_unstemmed | Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_short | Accelerated Verilog Simulator Using Application Specific Microprocessor |
| title_sort | accelerated verilog simulator using application specific microprocessor |
| topic | T Technology TK Electrical Engineering. Electronics. Nuclear Engineering |
| url | http://eprints.usm.my/45788/ http://eprints.usm.my/45788/1/Accelerated%20Verilog%20Simulator%20Using%20Application%20Specific%20Microprocessor.pdf |