Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga
Monte Carlo (MC) method is widely applied in mathematical problems that are extremely complicated to be resolved analytically. The method involves sampling process of the random numbers and probability to estimate the result. Since it depends on an enormous number of good quality random numbers t...
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| Format: | Thesis |
| Language: | English |
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2016
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| Online Access: | http://eprints.usm.my/45775/ http://eprints.usm.my/45775/1/Hardware%20Design%20Of%20Random%20Number%20Generator%20And%20Random%20Walk-Onboundary%20Algorithm%20To%20Compute%20Unit%20Cube%20Capacitance%20In%20Fpga.pdf |
| _version_ | 1848880422671351808 |
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| author | Niun, Cheah How |
| author_facet | Niun, Cheah How |
| author_sort | Niun, Cheah How |
| building | USM Institutional Repository |
| collection | Online Access |
| description | Monte Carlo (MC) method is widely applied in mathematical problems that are
extremely complicated to be resolved analytically. The method involves sampling
process of the random numbers and probability to estimate the result. Since it depends
on an enormous number of good quality random numbers to produce a high accuracy
result, developing a good random number generator (RNG) is vital. Generally, the
RNGs and the MC methods are implemented in software-based and simulated using
supercomputer and cluster Personal Computer (PC). Nevertheless, this
implementation consumes large expenses and inefficient space. With the latest
improvement of the density and speed of Field Programmable Gate Arrays (FPGA), a
direct implementation onto this hardware is feasible. This work aims to implement the
RNG and MC method of Random Walk on the Boundary (WOB) to compute the unit
cube capacitance on the target device Xilinx Spartan-6 LX 150T FPGA which were
incorporated in Avnet S6LX150T development board. Four uniform RNGs model
were evaluated to build the RNG, and the model that produced the most accurate
computation result was chosen for the implementation. From the evaluation, the result
has demonstrated that the RNG built from uniform RNG of 43-bit Linear Feedback
Shift Register (LFSR) and 37-bit Cellular Automata Shift Register (CASR) uniform
RNG combination produced the most accurate computation result. The
implementation of the MC computation and RNG to compute the unit cube capacitance
has been successfully carried out on the Xilinx Spartan-6 LX 150T FPGA. It therefore
demonstrates the feasibility of the FPGA as another hardware alternative for this kind
of work. |
| first_indexed | 2025-11-15T18:02:53Z |
| format | Thesis |
| id | usm-45775 |
| institution | Universiti Sains Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T18:02:53Z |
| publishDate | 2016 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | usm-457752020-10-22T03:03:17Z http://eprints.usm.my/45775/ Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga Niun, Cheah How T Technology TK7868.D5 Digital electronics and Electronic circuit design Monte Carlo (MC) method is widely applied in mathematical problems that are extremely complicated to be resolved analytically. The method involves sampling process of the random numbers and probability to estimate the result. Since it depends on an enormous number of good quality random numbers to produce a high accuracy result, developing a good random number generator (RNG) is vital. Generally, the RNGs and the MC methods are implemented in software-based and simulated using supercomputer and cluster Personal Computer (PC). Nevertheless, this implementation consumes large expenses and inefficient space. With the latest improvement of the density and speed of Field Programmable Gate Arrays (FPGA), a direct implementation onto this hardware is feasible. This work aims to implement the RNG and MC method of Random Walk on the Boundary (WOB) to compute the unit cube capacitance on the target device Xilinx Spartan-6 LX 150T FPGA which were incorporated in Avnet S6LX150T development board. Four uniform RNGs model were evaluated to build the RNG, and the model that produced the most accurate computation result was chosen for the implementation. From the evaluation, the result has demonstrated that the RNG built from uniform RNG of 43-bit Linear Feedback Shift Register (LFSR) and 37-bit Cellular Automata Shift Register (CASR) uniform RNG combination produced the most accurate computation result. The implementation of the MC computation and RNG to compute the unit cube capacitance has been successfully carried out on the Xilinx Spartan-6 LX 150T FPGA. It therefore demonstrates the feasibility of the FPGA as another hardware alternative for this kind of work. 2016-08 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/45775/1/Hardware%20Design%20Of%20Random%20Number%20Generator%20And%20Random%20Walk-Onboundary%20Algorithm%20To%20Compute%20Unit%20Cube%20Capacitance%20In%20Fpga.pdf Niun, Cheah How (2016) Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | T Technology TK7868.D5 Digital electronics and Electronic circuit design Niun, Cheah How Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga |
| title | Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga |
| title_full | Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga |
| title_fullStr | Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga |
| title_full_unstemmed | Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga |
| title_short | Hardware Design Of Random Number Generator And Random Walk-Onboundary Algorithm To Compute Unit Cube Capacitance In Fpga |
| title_sort | hardware design of random number generator and random walk-onboundary algorithm to compute unit cube capacitance in fpga |
| topic | T Technology TK7868.D5 Digital electronics and Electronic circuit design |
| url | http://eprints.usm.my/45775/ http://eprints.usm.my/45775/1/Hardware%20Design%20Of%20Random%20Number%20Generator%20And%20Random%20Walk-Onboundary%20Algorithm%20To%20Compute%20Unit%20Cube%20Capacitance%20In%20Fpga.pdf |