Clock Gating Technique For Power Reduction In Digital Design

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Clock Gating Technique For Power Reduction In Digital Design

Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not g...

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Bibliographic Details
Main Author:	Khor, Peng Lim
Format:	Thesis
Language:	English
Published:	2012
Subjects:	TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Online Access:	http://eprints.usm.my/44825/ http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf

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