Khor, P. L. (2012). Clock Gating Technique For Power Reduction In Digital Design.
Chicago Style (17th ed.) CitationKhor, Peng Lim. Clock Gating Technique For Power Reduction In Digital Design. 2012.
MLA (9th ed.) CitationKhor, Peng Lim. Clock Gating Technique For Power Reduction In Digital Design. 2012.
Warning: These citations may not always be 100% accurate.