The Development Of A Capacitive Parasitic Element
Extraction And Estimation Methodology To Improve
Design Cycle

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The Development Of A Capacitive Parasitic Element Extraction And Estimation Methodology To Improve Design Cycle

In the chip industry today, the key goals of a chip development organization is to develop and market chips within a short timeframe to gain foothold on market share. Despite this requirement, chip design and manufacturing are increasing in level of complexity due to advancement in process tec...

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Bibliographic Details
Main Author:	Teh, J-Me
Format:	Thesis
Language:	English
Published:	2013
Subjects:	TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Online Access:	http://eprints.usm.my/44002/ http://eprints.usm.my/44002/1/Teh%20J-Me24.pdf

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