Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect

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Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect

As the process technology advances, transistor size shrinks and more intellectual properties (IPs) are integrated onto chip. In order to accommodate the current complex functionalities as well as improving the performance of design, integrated circuit (IC) architecture has encouraged the integration...

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Bibliographic Details
Main Author:	Chiew , Chong Giap
Format:	Thesis
Language:	English
Published:	2016
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/41312/ http://eprints.usm.my/41312/1/CHIEW_CHONG_GIAP_24_Pages.pdf

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