Chiew , C. G. (2016). Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect.
Chicago Style (17th ed.) CitationChiew , Chong Giap. Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect. 2016.
MLA (9th ed.) CitationChiew , Chong Giap. Prelayout Design Of Configurable Serdes For High Speed Signaling In Multidie Interconnect. 2016.
Warning: These citations may not always be 100% accurate.