Design Rule Check To Validate Option Metal And Via For A Preprogrammed Layout Design - Oothayer Kumar, Sureindra Kumar (2014)

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Transistor sizing had been scaled down to increase the number of transistors in a single chip which also leads to the variation of IP blocks. Consequently, the layout design becomes very complex and it is challenging to verify the layout design. Therefore, the option layer had been identified where it will have a common base circuitry and layout. After the layout is completed, it is very convenient to convert the option metal and via to real metal and via layer. However, the conventional verification using the design rule check (DRC) in Cadence does not include the check for option layer. Option layer on preprogrammed layout are not verified correct and may cause a violation. Thus, this project will enable the verification of the option layer by developing an algorithm which able to cover the check for both option and real metal/via layer. This project will be based on TSMC 20nm process library and the modifications are made to enable the option layer check. In order to enable the modification to be made quickly and enable worst case check, Practical Extraction and Report Language (PERL) programming used to automate the code. The result is shown by drawing the test pattern with design rule. As example, a rule with specification of more than or equal with 0.05nm will flag an error if the test pattern is drawn less than 0.05nm. This approach had been applied to all the design rules involved in 20nm process technology. The method proposed validates the option layer successfully and most errors found in the early stage of designing the layout are minimized.