Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

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Modeling Of Vertical Side Chip Interconnect Technology For 3-Dimensional Packaging

In this miniaturization era, previously, shrinking the technology node was used in order to maintain and improve the electrical performance of a device. However, this method is getting difficult due to the limitation of Silicon (Si) atomic size of the material in designing the integrated circuit (IC...

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Bibliographic Details
Main Author:	Tan , Ai Heong
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK1-9971 Electrical engineering. Electronics. Nuclear engineering
Online Access:	http://eprints.usm.my/40931/ http://eprints.usm.my/40931/1/TAN_AI_HEONG_24_pages.pdf

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