Design and Implementation of I2C BUS Protocol on Xilinx FPGA - l Pradeep Kumar, Meenal (2017)

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The focal point of this research is to design and implement the Inter-Integrated Circuit (I2C) protocol with different types of features such as combined message, addressing mode, different data pattern, different start address, clock frequency, and type of mode between the FPGA and Test card. By using test card, signal integrity issue will be able to reduce as test card will be able to replicate the actual device. I2C IP is also able to reduce the cost and complexity issue as it consists of two signal. All of this features will able to randomize and run for long hours. The field-programmable gate array (FPGA) will act as master and test card as slave. As the design architecture consists of master and slave, the master will generates a START condition and at this condition the serial data (SDA) will have a transaction between high level to low level and serial clock (SCL) will remain high. Besides that, Master will also generate STOP condition. At STOP condition, SCL is HIGH and SDA will have a transaction from LOW to HIGH. Additionally, there are a few type of messaging mode such as read transaction, write transaction, write-read transaction and read-write transaction. All this messaging mode will have its own protocol. On the other hand, master also transfers and received data to or from slave devices by different addressing mode. The addressing mode that is implemented are 7 bit addressing mode and 10 bit addressing mode. This thesis is also concerned by randomizing the data byte send and start address. The data send, read and write particularly these operations are carried out and stimulate by capturing signal using logic analyzer. The signal is then examined and compared with the actual I2C protocol format. A stress test is also done by andomizing all the features and running for long hours which is 4 hours. This stress test is carried to stress the IP and make sure the IP is healthy