Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work
Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Tran...
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| Format: | Thesis |
| Language: | English |
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2017
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| Online Access: | http://eprints.usm.my/39594/ http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf |
| _version_ | 1848878789895913472 |
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| author | Pragasam, Matthew |
| author_facet | Pragasam, Matthew |
| author_sort | Pragasam, Matthew |
| building | USM Institutional Repository |
| collection | Online Access |
| description | Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Transfer Level (RTL) level to form a suspected boundary consisting of multiple logics from one end to the other, layout to schematic mapping automation tool helps to identify fault in design within given boundary. Therefore the development of a path extractor program which is capable of extracting all possible paths from these start to end signals can save engineers time in tracing components involved between a fault line. This feature is extremely significant in Electronic Design Automation (EDA) as it can provide results of net name sequences stored in a database of mapper files. These mapper files can be used in layout design debug as the net sequence represents schematic signals. To be able to retrieve all possible signals involved within a suspected boundary is a popular search computational problem. Therefore the path extractor program proposed incorporates the characteristics of a depth-first search algorithm by considering the specifications of a cell-based design. The objectives achieved in this research are proven reliable with path extraction results consistent even with search depth manipulation. Performance differs an average of 12.6 % (iteration count) with keeping maximum allowable depth of search constant. Paths of net sequences were consistent throughout the verification of the path extractor program. This development and study of the path extract method carries significance in areas of EDA and debug diagnosis work. |
| first_indexed | 2025-11-15T17:36:56Z |
| format | Thesis |
| id | usm-39594 |
| institution | Universiti Sains Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T17:36:56Z |
| publishDate | 2017 |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | usm-395942019-04-12T05:25:05Z http://eprints.usm.my/39594/ Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work Pragasam, Matthew TK1-9971 Electrical engineering. Electronics. Nuclear engineering Debug and diagnosis in post-silicon challenges the technological advancement in Physical-to-Layout Mapping capabilities. Areas that require such innovation are fault isolation work in failure analysis of semiconductor devices, at post-silicon stage. Since fault isolation work begins at Register Transfer Level (RTL) level to form a suspected boundary consisting of multiple logics from one end to the other, layout to schematic mapping automation tool helps to identify fault in design within given boundary. Therefore the development of a path extractor program which is capable of extracting all possible paths from these start to end signals can save engineers time in tracing components involved between a fault line. This feature is extremely significant in Electronic Design Automation (EDA) as it can provide results of net name sequences stored in a database of mapper files. These mapper files can be used in layout design debug as the net sequence represents schematic signals. To be able to retrieve all possible signals involved within a suspected boundary is a popular search computational problem. Therefore the path extractor program proposed incorporates the characteristics of a depth-first search algorithm by considering the specifications of a cell-based design. The objectives achieved in this research are proven reliable with path extraction results consistent even with search depth manipulation. Performance differs an average of 12.6 % (iteration count) with keeping maximum allowable depth of search constant. Paths of net sequences were consistent throughout the verification of the path extractor program. This development and study of the path extract method carries significance in areas of EDA and debug diagnosis work. 2017 Thesis NonPeerReviewed application/pdf en http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf Pragasam, Matthew (2017) Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work. Masters thesis, Universiti Sains Malaysia. |
| spellingShingle | TK1-9971 Electrical engineering. Electronics. Nuclear engineering Pragasam, Matthew Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work |
| title | Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work |
| title_full | Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work |
| title_fullStr | Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work |
| title_full_unstemmed | Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work |
| title_short | Very Large Scale Integration Cell Based Path Extractor For Physical To Layout Mapping In Fault Isolation Work |
| title_sort | very large scale integration cell based path extractor for physical to layout mapping in fault isolation work |
| topic | TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| url | http://eprints.usm.my/39594/ http://eprints.usm.my/39594/1/MATTHEW_PRAGASAM_24_Pages.pdf |