A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing
We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Hindawi Publishing Corporation
2010
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| Subjects: | |
| Online Access: | http://eprints.usm.my/38205/ http://eprints.usm.my/38205/1/A_Strategy_for_Automatic_Quality_Signing_and_Verification_Processes.pdf |
| _version_ | 1848878402882240512 |
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| author | Younis, Mohammed I. Zamli, Kamal Z. |
| author_facet | Younis, Mohammed I. Zamli, Kamal Z. |
| author_sort | Younis, Mohammed I. |
| building | USM Institutional Repository |
| collection | Online Access |
| description | We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here,
the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work,
the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite
during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification
Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test
suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can
potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study,
this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a
production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning
strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases. |
| first_indexed | 2025-11-15T17:30:46Z |
| format | Article |
| id | usm-38205 |
| institution | Universiti Sains Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T17:30:46Z |
| publishDate | 2010 |
| publisher | Hindawi Publishing Corporation |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | usm-382052018-01-03T07:57:38Z http://eprints.usm.my/38205/ A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing Younis, Mohammed I. Zamli, Kamal Z. TK1-9971 Electrical engineering. Electronics. Nuclear engineering We propose a novel strategy to optimize the test suite required for testing both hardware and software in a production line. Here, the strategy is based on two processes: Quality Signing Process and Quality Verification Process, respectively. Unlike earlier work, the proposed strategy is based on integration of black box and white box techniques in order to derive an optimum test suite during the Quality Signing Process. In this case, the generated optimal test suite significantly improves the Quality Verification Process. Considering both processes, the novelty of the proposed strategy is the fact that the optimization and reduction of test suite is performed by selecting only mutant killing test cases from cumulating t-way test cases. As such, the proposed strategy can potentially enhance the quality of product with minimal cost in terms of overall resource usage and time execution. As a case study, this paper describes the step-by-step application of the strategy for testing a 4-bit Magnitude Comparator Integrated Circuits in a production line. Comparatively, our result demonstrates that the proposed strategy outperforms the traditional block partitioning strategy with the mutant score of 100% to 90%, respectively, with the same number of test cases. Hindawi Publishing Corporation 2010 Article PeerReviewed application/pdf en http://eprints.usm.my/38205/1/A_Strategy_for_Automatic_Quality_Signing_and_Verification_Processes.pdf Younis, Mohammed I. and Zamli, Kamal Z. (2010) A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing. Advances in Software Engineering, 2010 (323429). pp. 1-7. ISSN 1687-8655 https://doi.org/10.1155/2010/323429 |
| spellingShingle | TK1-9971 Electrical engineering. Electronics. Nuclear engineering Younis, Mohammed I. Zamli, Kamal Z. A Strategy for Automatic Quality Signing and Verification Processes for Hardware and Software Testing |
| title | A Strategy for Automatic Quality Signing and Verification
Processes for Hardware and Software Testing |
| title_full | A Strategy for Automatic Quality Signing and Verification
Processes for Hardware and Software Testing |
| title_fullStr | A Strategy for Automatic Quality Signing and Verification
Processes for Hardware and Software Testing |
| title_full_unstemmed | A Strategy for Automatic Quality Signing and Verification
Processes for Hardware and Software Testing |
| title_short | A Strategy for Automatic Quality Signing and Verification
Processes for Hardware and Software Testing |
| title_sort | strategy for automatic quality signing and verification
processes for hardware and software testing |
| topic | TK1-9971 Electrical engineering. Electronics. Nuclear engineering |
| url | http://eprints.usm.my/38205/ http://eprints.usm.my/38205/ http://eprints.usm.my/38205/1/A_Strategy_for_Automatic_Quality_Signing_and_Verification_Processes.pdf |