Tolerating permanent faults in the input port of the network on chip router
Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of pro...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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MDPI
2019
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| Online Access: | http://psasir.upm.edu.my/id/eprint/77838/ http://psasir.upm.edu.my/id/eprint/77838/1/77838.pdf |
| _version_ | 1848858343914864640 |
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| author | Mohammed, Hala J. Flayyih, Wameedh Nazar Rokhani, Fakhrul Zaman |
| author_facet | Mohammed, Hala J. Flayyih, Wameedh Nazar Rokhani, Fakhrul Zaman |
| author_sort | Mohammed, Hala J. |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure. |
| first_indexed | 2025-11-15T12:11:57Z |
| format | Article |
| id | upm-77838 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T12:11:57Z |
| publishDate | 2019 |
| publisher | MDPI |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-778382020-05-04T16:57:26Z http://psasir.upm.edu.my/id/eprint/77838/ Tolerating permanent faults in the input port of the network on chip router Mohammed, Hala J. Flayyih, Wameedh Nazar Rokhani, Fakhrul Zaman Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure. MDPI 2019 Article PeerReviewed text en http://psasir.upm.edu.my/id/eprint/77838/1/77838.pdf Mohammed, Hala J. and Flayyih, Wameedh Nazar and Rokhani, Fakhrul Zaman (2019) Tolerating permanent faults in the input port of the network on chip router. Journal of Low Power Electronics and Applications, 9 (1). art. no. 11. pp. 1-18. ISSN 2079-9268 https://www.mdpi.com/2079-9268/9/1/11 10.3390/jlpea9010011 |
| spellingShingle | Mohammed, Hala J. Flayyih, Wameedh Nazar Rokhani, Fakhrul Zaman Tolerating permanent faults in the input port of the network on chip router |
| title | Tolerating permanent faults in the input port of the network on chip router |
| title_full | Tolerating permanent faults in the input port of the network on chip router |
| title_fullStr | Tolerating permanent faults in the input port of the network on chip router |
| title_full_unstemmed | Tolerating permanent faults in the input port of the network on chip router |
| title_short | Tolerating permanent faults in the input port of the network on chip router |
| title_sort | tolerating permanent faults in the input port of the network on chip router |
| url | http://psasir.upm.edu.my/id/eprint/77838/ http://psasir.upm.edu.my/id/eprint/77838/ http://psasir.upm.edu.my/id/eprint/77838/ http://psasir.upm.edu.my/id/eprint/77838/1/77838.pdf |