Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter

Power Amplifier (PA) plays a vital rule in wireless communication systems, it is used to amplify signal before transmission. Frequently, the PA needs to operate near the saturation region in order to achieve high efficiency power amplification. This will generate nonlinearities in the communication...

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Main Author: Saadoon, Mohammed Ayad
Format: Thesis
Language:English
Published: 2017
Subjects:
Online Access:http://psasir.upm.edu.my/id/eprint/70132/
http://psasir.upm.edu.my/id/eprint/70132/1/FK%202017%2094%20-%20IR.pdf
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author Saadoon, Mohammed Ayad
author_facet Saadoon, Mohammed Ayad
author_sort Saadoon, Mohammed Ayad
building UPM Institutional Repository
collection Online Access
description Power Amplifier (PA) plays a vital rule in wireless communication systems, it is used to amplify signal before transmission. Frequently, the PA needs to operate near the saturation region in order to achieve high efficiency power amplification. This will generate nonlinearities in the communication system, these nonlinearities will cause out of band distortion which increases the Adjacent Channel Leakage Ratio (ACLR) and in band distortion which increases the Bit Error Rate (BER). Likewise, the utilization of high spectrally efficient modulation techniques in modern communication systems such as Wideband Code Division Multiple Access (WCDMA) and Orthogonal Frequency Division Multiplexing (OFDM) that have high Peak to Average Power Ratio (PAPR) will be very vulnerable to PA nonlinearities and as the signal bandwidth gets wider, the PA will exhibit memory effects which will cause dynamic distortions in the PA characteristics. Therefore, linearization of the PA is required to overcome these effects. Digital Pre-Distortion (DPD), among all linearization techniques, is a low-cost and efficient method to linearize PAs exhibiting memory effects. However, the recent DPD schemes require time to find the PA inverse characteristics to be predistorted; so, in order to quickly adapt with the dynamic changes in the PA characteristics, a DPD with fast convergence is highly desirable. In this thesis, a new DPD technique is proposed for fast linearization of power amplifiers exhibiting memory effects. The proposed technique combines Memory Polynomial (MP) model and linearly interpolated Look-up Table (LUT) predistorters that are cascaded in series to form the proposed predistorter model. The LUT addresses the highly nonlinearity distortion of the PA, while the MP compensates mild nonlinearities and memory effects. Moreover, by utilizing the linear interpolation technique to index the LUT and indirect learning architecture to extract the MP coefficients, faster convergence is achieved. The performance of the proposed technique is verified through simulation in Matlab program using a real class-AB power amplifier, driven by two WCDMA signals of 5-MHz and 15-MHz bandwidths. The simulation results show approximately 12 dB improvement in the ACLR reduction as compared to the MP model and the overall reduction was about 30 to 35 dB. Also, about 0.3% EVM performance was achieved and the PA dynamic memory effects were compensated using the proposed model. This work shows that a high linearity performance for the PA is achieved with the proposed technique. Thus, the distortion in the output signal was removed and therefore, an improved power efficiency is attained with reduction in the transmitter power consumption.
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format Thesis
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institution Universiti Putra Malaysia
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language English
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publishDate 2017
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spelling upm-701322019-08-16T00:40:07Z http://psasir.upm.edu.my/id/eprint/70132/ Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter Saadoon, Mohammed Ayad Power Amplifier (PA) plays a vital rule in wireless communication systems, it is used to amplify signal before transmission. Frequently, the PA needs to operate near the saturation region in order to achieve high efficiency power amplification. This will generate nonlinearities in the communication system, these nonlinearities will cause out of band distortion which increases the Adjacent Channel Leakage Ratio (ACLR) and in band distortion which increases the Bit Error Rate (BER). Likewise, the utilization of high spectrally efficient modulation techniques in modern communication systems such as Wideband Code Division Multiple Access (WCDMA) and Orthogonal Frequency Division Multiplexing (OFDM) that have high Peak to Average Power Ratio (PAPR) will be very vulnerable to PA nonlinearities and as the signal bandwidth gets wider, the PA will exhibit memory effects which will cause dynamic distortions in the PA characteristics. Therefore, linearization of the PA is required to overcome these effects. Digital Pre-Distortion (DPD), among all linearization techniques, is a low-cost and efficient method to linearize PAs exhibiting memory effects. However, the recent DPD schemes require time to find the PA inverse characteristics to be predistorted; so, in order to quickly adapt with the dynamic changes in the PA characteristics, a DPD with fast convergence is highly desirable. In this thesis, a new DPD technique is proposed for fast linearization of power amplifiers exhibiting memory effects. The proposed technique combines Memory Polynomial (MP) model and linearly interpolated Look-up Table (LUT) predistorters that are cascaded in series to form the proposed predistorter model. The LUT addresses the highly nonlinearity distortion of the PA, while the MP compensates mild nonlinearities and memory effects. Moreover, by utilizing the linear interpolation technique to index the LUT and indirect learning architecture to extract the MP coefficients, faster convergence is achieved. The performance of the proposed technique is verified through simulation in Matlab program using a real class-AB power amplifier, driven by two WCDMA signals of 5-MHz and 15-MHz bandwidths. The simulation results show approximately 12 dB improvement in the ACLR reduction as compared to the MP model and the overall reduction was about 30 to 35 dB. Also, about 0.3% EVM performance was achieved and the PA dynamic memory effects were compensated using the proposed model. This work shows that a high linearity performance for the PA is achieved with the proposed technique. Thus, the distortion in the output signal was removed and therefore, an improved power efficiency is attained with reduction in the transmitter power consumption. 2017-06 Thesis NonPeerReviewed text en http://psasir.upm.edu.my/id/eprint/70132/1/FK%202017%2094%20-%20IR.pdf Saadoon, Mohammed Ayad (2017) Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter. Masters thesis, Universiti Putra Malaysia. Power amplifiers Digital control systems
spellingShingle Power amplifiers
Digital control systems
Saadoon, Mohammed Ayad
Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
title Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
title_full Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
title_fullStr Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
title_full_unstemmed Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
title_short Linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
title_sort linearization of power amplifiers with memory effects using memory polynomial and linearly interpolated look-up table predistorter
topic Power amplifiers
Digital control systems
url http://psasir.upm.edu.my/id/eprint/70132/
http://psasir.upm.edu.my/id/eprint/70132/1/FK%202017%2094%20-%20IR.pdf