A new cascaded multilevel inverter topology with minimum number of conducting switches
There are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality. The main drawback for this type of inverter is the high number of switching device it needs in an installation. In order to reduce total harmonics distortion (...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2014
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| Online Access: | http://psasir.upm.edu.my/id/eprint/69211/ http://psasir.upm.edu.my/id/eprint/69211/1/A%20new%20cascaded%20multilevel%20inverter%20topology%20with%20minimum%20number%20of%20conducting%20switches.pdf |
| _version_ | 1848856340569522176 |
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| author | Mohamad, Ahmad Syukri Mariun, Norman Sulaiman, Nasri Mohd Radzi, Mohd Amran |
| author_facet | Mohamad, Ahmad Syukri Mariun, Norman Sulaiman, Nasri Mohd Radzi, Mohd Amran |
| author_sort | Mohamad, Ahmad Syukri |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | There are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality. The main drawback for this type of inverter is the high number of switching device it needs in an installation. In order to reduce total harmonics distortion (THD) of the output voltage waveform, the number of output voltage level need to be increased, hence the higher number of switching devices. This subsequently increases the installation cost, inverter circuit size and power losses - in the form of heat and voltage losses in the inverter circuit. In this paper a new cascaded multilevel inverter topology is proposed with a minimum number of switching devices and driver circuits needed. The proposed new topology also needs to turn on only three switching devices at any operation time for any output voltage level configurations. The new cascaded multilevel inverter topology validity is verified by the simulation and experimental results of a prototype single phase 41-level inverter. The prototype inverter can also be designed to supply a load with a specific power factor requirement. |
| first_indexed | 2025-11-15T11:40:06Z |
| format | Conference or Workshop Item |
| id | upm-69211 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T11:40:06Z |
| publishDate | 2014 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-692112019-06-12T07:37:45Z http://psasir.upm.edu.my/id/eprint/69211/ A new cascaded multilevel inverter topology with minimum number of conducting switches Mohamad, Ahmad Syukri Mariun, Norman Sulaiman, Nasri Mohd Radzi, Mohd Amran There are many advantages of the cascaded multilevel inverter such as low voltage stress for each switching device and higher power quality. The main drawback for this type of inverter is the high number of switching device it needs in an installation. In order to reduce total harmonics distortion (THD) of the output voltage waveform, the number of output voltage level need to be increased, hence the higher number of switching devices. This subsequently increases the installation cost, inverter circuit size and power losses - in the form of heat and voltage losses in the inverter circuit. In this paper a new cascaded multilevel inverter topology is proposed with a minimum number of switching devices and driver circuits needed. The proposed new topology also needs to turn on only three switching devices at any operation time for any output voltage level configurations. The new cascaded multilevel inverter topology validity is verified by the simulation and experimental results of a prototype single phase 41-level inverter. The prototype inverter can also be designed to supply a load with a specific power factor requirement. IEEE 2014 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/69211/1/A%20new%20cascaded%20multilevel%20inverter%20topology%20with%20minimum%20number%20of%20conducting%20switches.pdf Mohamad, Ahmad Syukri and Mariun, Norman and Sulaiman, Nasri and Mohd Radzi, Mohd Amran (2014) A new cascaded multilevel inverter topology with minimum number of conducting switches. In: 2014 IEEE Innovative Smart Grid Technologies - Asia (ISGT ASIA), 20-23 May 2014, Berjaya Times Square Hotel, Kuala Lumpur, Malaysia. (pp. 164-169). 10.1109/ISGT-Asia.2014.6873783 |
| spellingShingle | Mohamad, Ahmad Syukri Mariun, Norman Sulaiman, Nasri Mohd Radzi, Mohd Amran A new cascaded multilevel inverter topology with minimum number of conducting switches |
| title | A new cascaded multilevel inverter topology with minimum number of conducting switches |
| title_full | A new cascaded multilevel inverter topology with minimum number of conducting switches |
| title_fullStr | A new cascaded multilevel inverter topology with minimum number of conducting switches |
| title_full_unstemmed | A new cascaded multilevel inverter topology with minimum number of conducting switches |
| title_short | A new cascaded multilevel inverter topology with minimum number of conducting switches |
| title_sort | new cascaded multilevel inverter topology with minimum number of conducting switches |
| url | http://psasir.upm.edu.my/id/eprint/69211/ http://psasir.upm.edu.my/id/eprint/69211/ http://psasir.upm.edu.my/id/eprint/69211/1/A%20new%20cascaded%20multilevel%20inverter%20topology%20with%20minimum%20number%20of%20conducting%20switches.pdf |