Design of 8-bit SAR-ADC CMOS
Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18μm CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic...
| Main Authors: | , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
IEEE
2009
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| Online Access: | http://psasir.upm.edu.my/id/eprint/68879/ http://psasir.upm.edu.my/id/eprint/68879/1/Design%20of%208-bit%20SAR-ADC%20CMOS.pdf |
| _version_ | 1848856251538079744 |
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| author | Hassan, Hur A. Abdul Halin, Izhal Aris, Ishak Hassan, Mohd Khair |
| author_facet | Hassan, Hur A. Abdul Halin, Izhal Aris, Ishak Hassan, Mohd Khair |
| author_sort | Hassan, Hur A. |
| building | UPM Institutional Repository |
| collection | Online Access |
| description | Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18μm CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs. |
| first_indexed | 2025-11-15T11:38:41Z |
| format | Conference or Workshop Item |
| id | upm-68879 |
| institution | Universiti Putra Malaysia |
| institution_category | Local University |
| language | English |
| last_indexed | 2025-11-15T11:38:41Z |
| publishDate | 2009 |
| publisher | IEEE |
| recordtype | eprints |
| repository_type | Digital Repository |
| spelling | upm-688792019-06-11T02:02:23Z http://psasir.upm.edu.my/id/eprint/68879/ Design of 8-bit SAR-ADC CMOS Hassan, Hur A. Abdul Halin, Izhal Aris, Ishak Hassan, Mohd Khair Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18μm CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs. IEEE 2009 Conference or Workshop Item PeerReviewed text en http://psasir.upm.edu.my/id/eprint/68879/1/Design%20of%208-bit%20SAR-ADC%20CMOS.pdf Hassan, Hur A. and Abdul Halin, Izhal and Aris, Ishak and Hassan, Mohd Khair (2009) Design of 8-bit SAR-ADC CMOS. In: 2009 IEEE Student Conference on Research and Development (SCOReD 2009), 16-18 Nov. 2009, UPM, Serdang, Selangor. (pp. 272-275). 10.1109/SCORED.2009.5443038 |
| spellingShingle | Hassan, Hur A. Abdul Halin, Izhal Aris, Ishak Hassan, Mohd Khair Design of 8-bit SAR-ADC CMOS |
| title | Design of 8-bit SAR-ADC CMOS |
| title_full | Design of 8-bit SAR-ADC CMOS |
| title_fullStr | Design of 8-bit SAR-ADC CMOS |
| title_full_unstemmed | Design of 8-bit SAR-ADC CMOS |
| title_short | Design of 8-bit SAR-ADC CMOS |
| title_sort | design of 8-bit sar-adc cmos |
| url | http://psasir.upm.edu.my/id/eprint/68879/ http://psasir.upm.edu.my/id/eprint/68879/ http://psasir.upm.edu.my/id/eprint/68879/1/Design%20of%208-bit%20SAR-ADC%20CMOS.pdf |