A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis

A process variation aware system-level framework to model on-chip communication system in support of fault tolerant analysis

On-chip interconnect communication system consists of the drivers, interconnect wires and receivers. Several on-chip communication system models have been developed for the purpose of on-chip fault-tolerant communication research. While most of these models improved the channel modeling, the effects...

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Bibliographic Details
Main Authors: Forooshani, Arash Abtahi, Rokhani, Fakhrul Zaman, Samsudin, Khairulmizam, Abd Aziz, Samsuzana
Format: Conference or Workshop Item
Language:English
Published: IEEE 2009
Online Access:http://psasir.upm.edu.my/id/eprint/68595/
http://psasir.upm.edu.my/id/eprint/68595/1/A%20process%20variation%20aware%20system-level%20framework%20to%20model%20on-chip%20communication%20system%20in%20support%20of%20fault%20tolerant%20analysis.pdf

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